This configurable use logic block can serve as either a 2-bit LUT, or as a D flip-flop/latch.

Figure 7-4 2-Bit LUT or DFF or Latch Block Diagram

When used to implement LUT functions, the 2-bit LUT takes in two input signals from the connection mux and produces a single output, which goes back into the connection mux. These LUTs can be configured to any 2-input user defined function, including the following standard digital logic functions: AND, NAND, OR, NOR, XOR, XNOR, INV.

Table 7-4 provides the truth table for a 2-bit LUT.

Each 2-bit LUT has 4 bits in the OTP to define their output function.

When used to implement a sequential logic element, the two input signals from the connection mux go to the data (D) and clock (CLK) inputs of the flip-flop/latch, with the output going back to the connection mux. This macro-cell has initial state parameters, as well as clock and output polarity parameters.

The operation of the D flip-flop/latch will follow the following functional descriptions:

• The clock polarity is configurable and can be set to non-inverted (CLKPOL = 0, CLK) or inverted (CLKPOL = 1, nCLK).
  • DFF with CLK: CLK is rising edge triggered, then Q = D; otherwise Q will not change.
  • DFF with nCLK: CLK is falling edge triggered, then Q = D; otherwise Q will not change.
  • Latch with CLK: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is High).
  • Latch with nCLK: when CLK is High, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is Low).
• The output polarity is configurable and can be set to non-inverted (Q) or inverted (nQ).

Table 7-5 and Table 7-6 provides the truth tables for the D flip-flop and D latch, respectively.