Figure 54 through Figure 57 shows an example PCB layout and the following list provides a description of each layer.
The top layer has all components and the main traces for VIN, SW, VOUT and PGND. Both VIN pins are bypassed with two input capacitors placed as close as possible to the IC and are connected directly to the adjacent PGND pins. Multiple vias are placed near the input and output capacitors. The AGND trace is connected to PGND with a wide trace away from the input capacitors to minimize switching noise.
Midlayer 1 has a solid PGND plane to connect the PGND pins on both sides of the IC together with the shortest path possible and to aid with thermal performance.
Midlayer 2 has a wide trace connecting both VIN pins of the IC. It is also used to route the BOOT pin to the BOOT-SW capacitor (CBT). It also has a parallel trace for VOUT to minimize trace resistance. The rest of this layer is covered with PGND.
The bottom layer has the trace connecting the FB resistor divider to VOUT at the point of regulation. PGND is filled into the rest of this layer to aid with thermal performance.