SLVSDV8 July 2017 TPS54424
An internal Phase Locked Loop (PLL) has been implemented to allow synchronization from 200 kHz to 1600 kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle from 20% to 80%. If the clock signals rising edge occurs near the falling edge of SW, increased SW jitter may occur. Use Equation 11 to calculate the maximum clock pulse width to minimize jitter in CLK mode. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The start of the switching cycle is synchronized to the falling edge of the RT/CLK pin.
In applications where both RT mode and CLK mode are needed, the device can be configured as shown in Figure 31. Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the SYNC pin is pulled above the RT/CLK high threshold (2 V), the device switches from the RT mode to the CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock.
If the input clock goes away the internal clock frequency begins to drop and after 10 µs without a clock the device returns to RT mode. Output undershoot while the switching frequency drops can occur. Output overshoot can also occur when the switching frequency steps back up to the RT mode frequency. A high impedance tri-state buffer as shown in Figure 33 is recommended for best performance during the transition from CLK mode to RT mode because it minimizes the loading on the RT/CLK pin allowing faster transition back to RT mode. Figure 34 shows the typical performance for the transition from RT mode to CLK mode then back to RT mode.
A series RC circuit as shown in Figure 32 can also be used to interface the RT/CLK pin but the capacitive load slows down the transition back to RT mode. The series RC circuit is not recommended if the transition from CLK mode to RT mode is important. A capacitor in the range of 47 pF to 470 pF is recommended. When using the series RC circuit verify the amplitude of the signal at the RT/CLK pin goes above the high threshold.