SLVSFQ9A August   2021  – November 2021 TPSM8A28 , TPSM8A29

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using External Bias on VCC Pin
      2. 7.3.2  Enable
      3. 7.3.3  Output Voltage Setting
        1. 7.3.3.1 Remote Sense
      4. 7.3.4  Internal Fixed Soft Start and External Adjustable Soft Start
      5. 7.3.5  External REFIN for Output Voltage Tracking
      6. 7.3.6  Frequency and Operation Mode Selection
      7. 7.3.7  D-CAP3™ Control
      8. 7.3.8  Low-Side FET Zero-Crossing
      9. 7.3.9  Current Sense and Positive Overcurrent Protection
      10. 7.3.10 Low-Side FET Negative Current Limit
      11. 7.3.11 Power Good
      12. 7.3.12 Overvoltage and Undervoltage Protection
      13. 7.3.13 Out-Of-Bounds (OOB) Operation
      14. 7.3.14 Output Voltage Discharge
      15. 7.3.15 UVLO Protection
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-Mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Powering the Device From a 12-V Bus
      4. 7.4.4 Powering the Device From a 5.0-V Bus
      5. 7.4.5 Powering the Device From a Split-Rail Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Output Voltage Setting Point
        2. 8.2.2.2  Choose the Inductor
        3. 8.2.2.3  Set the Current Limit (TRIP)
        4. 8.2.2.4  Choose the Output Capacitor
        5. 8.2.2.5  Choose the Input Capacitors (CIN)
        6. 8.2.2.6  Soft-Start Capacitor (SS/REFIN Pin)
        7. 8.2.2.7  EN Pin Resistor Divider
        8. 8.2.2.8  VCC Bypass Capacitor
        9. 8.2.2.9  BOOT Capacitor
        10. 8.2.2.10 PGOOD Pullup Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Performance on the TI EVM
    3. 10.3 EMI
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to +125°C, VCC = Internal 4.5V LDO, both TPSM8A29 and TPSM8A28 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IQ_VIN VIN operating nonswitching supply current VEN = 2 V, VFB = 0.65 V, VIN = 12 V, no external bias on the VCC pin 680 850 µA
ISD_VIN VIN shutdown supply current VEN = 0 V, VIN =12 V, no external bias on the VCC pin 9.5 20 µA
IQ_VCC VCC quiescent current TJ = 25°C, VEN = 2 V, VFB = 0.65 V, VIN = 5 V, 5.0 V external bias on the VCC pin 680 820 µA
ISD_VCC VCC shutdown current TJ = 25°C, VEN = 0 V, VIN = 0 V, 5.0 V external bias on the VCC pin 75 85 µA
REFERENCE VOLTAGE
VINTREF Internal REF voltage TJ = 25°C 600 mV
Internal REF voltage tolerance TJ = 0°C to 70°C 597 603 mV
Internal REF voltage tolerance TJ = –40°C to 125°C 594 606 mV
IFB FB input current VFB = VINTREF 50 100 nA
OUTPUT DISCHARGE
RDischg Output discharge resistance VIN = 12 V, VCC = internal LDO, Vsw = 0.5 V, power conversion disabled 70 Ω
SWITCHING FREQUENCY
fSW VO switching frequency, FCCM operation VIN = 12 V, VOUT = 1.2 V, RMODE = 0 Ω to AGND 490 620 750 kHz
VIN = 12 V, VOUT = 1.2 V, RMODE = 30.1 kΩ to AGND 720 800 880
VIN = 12 V, VOUT = 1.2 V, RMODE = 60.4 kΩ to AGND 840 1000 1250
tON(min) Minimum on time TJ = 25°C(1) 70 85 ns
tOFF(min) Minimum off time TJ = 25°C, HS FET gate falling to rising(1) 220 ns
ENABLE
VENH EN enable threshold voltage (rising) 1.17 1.22 1.27 V
VENL EN disable threshold voltage (falling) 0.97 1.02 1.07 V
VENHYST EN hysteresis voltage 0.2 V
VENLEAK EN input leakage current VEN = V 0.5 5 µA
EN internal pulldown resistance EN pin to AGND. EN floating disables the converter. 6500 kΩ
INTERNAL VCC LDO
VCC Internal LDO output voltage VIN = 12 V, ILOAD = 2 mA 4.32 4.5 4.68 V
VCCUVLO VCC undervoltage-lockout (UVLO) threshold voltage VCC rising 2.80 2.87 2.94 V
VCC falling 2.62 2.7 2.77 V
VCCUVLO VCC undervoltage-lockout (UVLO) threshold voltage VCC hysteresis 0.17 V
VCCDO LDO low-droop dropout voltage VIN = 3.0 V, IVCC_LOAD = 2 mA, TJ = 25°C 62 75 mV
LDO overcurrent limit All VINs, all temperature 105 158 mA
STARTUP
tSS Soft-start time VO rising from 0 V to 95% of final setpoint, CSS/REFIN = open 1 1.5 ms
SS/REFIN sourcing current VSS/REFIN = 0 V 36 µA
SS/REFIN sinking current VSS/REFIN = 1 V 12 µA
EN to first switching delay, internal LDO The delay from EN goes high to the first SW rising edge with internal LDO configuration. CVCC = 2.2 µF. CSS/REFIN = 220 nF 0.93 2 ms
EN to first switching delay, external VCC bias The delay from EN goes high to the first SW rising edge with external VCC bias configuration. VCC bias must reach regulation before EN ramp up. CSS/REFIN = 220 nF. 550 900 µs
PGOOD COMPARATOR
VPGTH PGOOD threshold FB rising, PGOOD low to high 89% 92.5% 95%
FB rising, PGOOD high to low 113% 116% 119%
FB falling, PGOOD high to low 77% 80% 83%
VPGTH OOB (out-of-bounds) threshold FB rising, PGOOD stays high 103% 105.5% 108%
IPG PGOOD sink current VPGOOD = 0.4 V, VIN = 12 V, VCC = Internal LDO 25 mA
IPG PGOOD low-level output voltage IPGOOD = 5.5 mA, VIN = 12 V, VCC = internal LDO 400 mV
tPG_delay PGOOD delay time Delay for PGOOD from low to high 1.0 1.4 ms
Delay for PGOOD from high to low 0.5 5 µs
IPG_lkg PGOOD leakage current when pulled high TJ = 25°C, VPGOOD = 3.3 V, VFB = VINTREF 5 µA
PGOOD clamp low-level output voltage VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD pulled up to 3.3 V through a 100-kΩ resistor 710 850 mV
VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD pulled up to 3.3 V through a 10-kΩ resistor 850 1000 mV
Minimum VCC for valid PGOOD output 1.5 V
OVERCURRENT PROTECTION
RTRIP TRIP pin resistance range TPSM8A28 4.02 14.7 kΩ
RTRIP TRIP pin resistance range TPSM8A29 0 14.7 kΩ
IOCL Current limit threshold, TPSM8A29 only Valley current on LS FET, 0 kΩ ≤ RTRIP ≤ 3.3 kΩ TPSM8A29 only 14.8 18.4 21.7 A
IOCL Current limit threshold Valley current on LS FET, RTRIP = 4.02 kΩ 12.0 14.2 16.3 A
IOCL Current limit threshold Valley current on LS FET, RTRIP = 4.99 kΩ 9.9 12.0 14.1 A
IOCL Current limit threshold Valley current on LS FET, RTRIP = 10 kΩ 3.9 6.0 8.1 A
KOCL KOCL for RTRIP equation 60000 A Ω
INOCL Negative current limit threshold All VINs –12 –10 –8 A
IZC Zero-cross detection current threshold, open loop VIN = 12 V, VCC = Internal LDO 400 mA
UVLO
VINUVLO VIN UVLO threshold voltage Rising 2.1 2.4 2.7 V
Falling 1.55 1.85 2.15 V
VOVP Overvoltage-protection (OVP) threshold voltage 113% 116% 119%
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold(1) Temperature rising 165 °C
Thermal shutdown hysteresis(1) 30 °C
(1) Specified by design. Not production tested.