SLOSEF7 July   2025 TRF1305C1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - AC Specifications in D2D Configuration
    6. 6.6 Electrical Characteristics - AC Specifications in S2D Configuration
    7. 6.7 Electrical Characteristics - DC and Timing Specifications
    8. 6.8 Typical Characteristics: D2D Configuration
    9. 6.9 Typical Characteristics: S2D Configuration
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Differential RF Amplifier
      2. 7.3.2 Output Common-Mode Control
      3. 7.3.3 Internal Resistor Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
        1. 7.4.1.1 Input Common-Mode Extension
      2. 7.4.2 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Interface Considerations
        1. 8.1.1.1 Single-Ended Input
        2. 8.1.1.2 Differential Input
        3. 8.1.1.3 DC-Coupling Considerations
      2. 8.1.2 Gain Adjustment With External Resistors in a Differential Input Configuration
    2. 8.2 Typical Application
      1. 8.2.1 TRF1305C1 as ADC Driver in a Zero-IF Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Supply Voltages
      2. 8.3.2 Single-Supply Operation
      3. 8.3.3 Split-Supply Operation
      4. 8.3.4 Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RPV|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9 Typical Characteristics: S2D Configuration

at TA = 25℃, VS+ = 5V, VS– = 0V, floating VOCM, PD, and MODE pins, VICM = mid-supply, S2D ac-coupled input/output configuration with RTERM = 50Ω, ZS = 50Ω, ZL = 100Ω (see Figure 8-1), input and outputs de-embedded up to the device pins, and ambient temperatures shown (unless otherwise noted)

TRF1305C1 Power Gain (Sds21) Across Temperature
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-51 Power Gain (Sds21) Across Temperature
TRF1305C1 Input Return Loss (Sss11) Across Temperature
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-53 Input Return Loss (Sss11) Across Temperature
TRF1305C1 Output Return Loss (Sdd22) Across Temperature
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-55 Output Return Loss (Sdd22) Across Temperature
TRF1305C1 Reverse Isolation (Ssd12) Across Temperature
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-57 Reverse Isolation (Ssd12) Across Temperature
TRF1305C1 OIP3 Across Temperature
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-59 OIP3 Across Temperature
TRF1305C1 OIP3 Across Temperature
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-61 OIP3 Across Temperature
TRF1305C1 IMD3 Lower Across Temperature
At (2f1 – f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-63 IMD3 Lower Across Temperature
TRF1305C1 IMD3 Higher Across Temperature
At (2f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-65 IMD3 Higher Across Temperature
TRF1305C1 IMD3 Lower Across Temperature
At (2f1 – f2) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-67 IMD3 Lower Across Temperature
TRF1305C1 IMD3 Higher Across Temperature
At (2f2 – f1) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-69 IMD3 Higher Across Temperature
TRF1305C1 OIP2 Across Temperature
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-71 OIP2 Across Temperature
TRF1305C1 OIP2 Across Temperature
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-73 OIP2 Across Temperature
TRF1305C1 IMD2 Across Temperature
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-75 IMD2 Across Temperature
TRF1305C1 IMD2 Across Temperature
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-77 IMD2 Across Temperature
TRF1305C1 HD2 Across Output Power and Temperature
 
Figure 6-79 HD2 Across Output Power and Temperature
TRF1305C1 HD3 Across Output Power and Temperature
 
Figure 6-81 HD3 Across Output Power and Temperature
TRF1305C1 OP1dB Across Temperature
 
Figure 6-83 OP1dB Across Temperature
TRF1305C1 Noise Figure Across Temperature
 
Figure 6-85 Noise Figure Across Temperature
TRF1305C1 Step Response
DC-coupled, VS+ = 2.5V, VS– = –2.5V
Figure 6-87 Step Response
TRF1305C1 Differential Output Power Across Single Ended Input Power
 
Figure 6-89 Differential Output Power Across Single Ended Input Power
TRF1305C1 Amplitude and Phase Imbalance
PIN = –20dBm at each driven input pin with 50Ω source
 
Figure 6-91 Amplitude and Phase Imbalance
TRF1305C1 Power Gain (Sds21) Across Supply Voltage
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-52 Power Gain (Sds21) Across Supply Voltage
TRF1305C1 Input Return Loss (Sss11) Across Supply Voltage
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-54 Input Return Loss (Sss11) Across Supply Voltage
TRF1305C1 Output Return Loss (Sdd22) Across Supply Voltage
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-56 Output Return Loss (Sdd22) Across Supply Voltage
TRF1305C1 Reverse Isolation (Ssd12) Across Supply Voltage
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-58 Reverse Isolation (Ssd12) Across Supply Voltage
TRF1305C1 OIP3 Across Supply Voltage
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-60 OIP3 Across Supply Voltage
TRF1305C1 OIP3 Across Supply Voltage
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-62 OIP3 Across Supply Voltage
TRF1305C1 IMD3 Lower Across Supply Voltage
At (2f1 – f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-64 IMD3 Lower Across Supply Voltage
TRF1305C1 IMD3 Higher Across Supply Voltage
At (2f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-66 IMD3 Higher Across Supply Voltage
TRF1305C1 IMD3 Lower Across Supply Voltage
At (2f1 – f2) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-68 IMD3 Lower Across Supply Voltage
TRF1305C1 IMD3 Higher Across Supply Voltage
At (2f2 – f1) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-70 IMD3 Higher Across Supply Voltage
TRF1305C1 OIP2 Across Supply Voltage
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-72 OIP2 Across Supply Voltage
TRF1305C1 OIP2 Across Supply Voltage
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-74 OIP2 Across Supply Voltage
TRF1305C1 IMD2 Across Supply Voltage
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-76 IMD2 Across Supply Voltage
TRF1305C1 IMD2 Across Supply Voltage
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-78 IMD2 Across Supply Voltage
TRF1305C1 HD2 Across Output Power and Supply Voltage
 
Figure 6-80 HD2 Across Output Power and Supply Voltage
TRF1305C1 HD3 Across Output Power and Supply Voltage
 
Figure 6-82 HD3 Across Output Power and Supply Voltage
TRF1305C1 OP1dB Across Supply Voltage
 
Figure 6-84 OP1dB Across Supply Voltage
TRF1305C1 Noise Figure Across Supply Voltage
 
Figure 6-86 Noise Figure Across Supply Voltage
TRF1305C1 Power Up and Power Down Timing
DC-coupled, VS+ = 2.5V, VS– = –2.5V
Figure 6-88 Power Up and Power Down Timing
TRF1305C1 Common-Mode Rejection Ratio (CMRR)
PIN = –20dBm at each driven input pin with 50Ω source
Figure 6-90 Common-Mode Rejection Ratio (CMRR)
TRF1305C1 Overdrive Recovery Response
DC-coupled, VS+ = 2.5V, VS– = –2.5V, 2X to 5X output voltages have input voltages 2 to 5 times VIN
Figure 6-92 Overdrive Recovery Response