SNLS696A April 2021 – May 2021 TSER953
The serial control bus consists of two signals: SCL and SDA. SCL is a Serial Bus Clock Input / Output signal and the SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pullup resistor to VI2C, chosen to be either 1.8 V or 3.3 V.
For the standard and fast I2C modes, a pullup resistor of RPU = 4.7 kΩ is recommended, while a pullup resistor of RPU = 470 Ω is recommended for the fast plus mode. However, the pullup resistor value may be additionally adjusted for capacitive loading and data rate requirements. The signals are either pulled High or driven Low. The IDX pin configures the control interface to one of two possible device addresses. A pullup resistor (RHIGH) and a pulldown resistor (RLOW) may be used to set the appropriate voltage on the IDX input pin.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SDA transitions Low while SCL is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See Figure 7-9.
To communicate with an I2C slave, the host controller (master) sends data to the slave address and waits for a response. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, the slave Acknowledges (ACKs) the master by driving the SDA bus low. If the address does not match a slave address of the device, the slave Not-acknowledges (NACKs) the master by pulling the SDA High. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know that the master wants to receive another data byte. When the master wants to stop reading, the master NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a start condition or a repeated start condition. All communication on the bus ends with a stop condition. A READ is shown in Figure 7-10 and a WRITE is shown in Figure 7-11.
Any I2C master located at the serializer must support I2C clock stretching. For more information on I2C interface requirements and throughput considerations, refer to the TI application note I2C communication over FPD-Link III with bidirectional control channel (SNLA131).