SNLS696A April 2021 – May 2021 TSER953
|7:0||SCL_HIGH_TIME||R/W||0x7F||I2C Master SCL High Time. |
This field configures the high pulse width of the SCL output when the Serializer is the Master on the local I2C bus. Units are 38.1 ns for the nominal oscillator clock frequency of 26.25 MHz. The default value is set to provide a minimum 5-µs SCL high time with the internal oscillator clock running at 26.25 MHz. Delay includes 5 additional oscillator clock periods.
Min_delay = 38.0952 ns × (SCL_HIGH_TIME + 5)