SNLS696A April 2021 – May 2021 TSER953
The TSER953 can be placed into DVP mode to pair with DVP mode deserializers. While the mode should have been configured using the Mode pin on the TSER953, the register MODE_SEL register 0x03[2:0] can be used to verify or override the current mode. This field always indicates the mode setting of the device. When bit 4 of this register is 0, this field is read-only and shows the mode setting. Mode is latched from strap value when PDB transitions LOW to HIGH, and the value should read back 101 (0x5) if the resistive strap is set correctly to DVP external clock mode. Alternatively, when bit 4 of this register is set to 1, the MODE field is read/write and can be programmed to 101 to assign the correct DVP compatible MODE. This is shown in Table 7-14.
CSI-2 input data provided to the TSER953 must be synchronized to the input frequency applied to CLKIN when using DVP external clock mode. The PCLK frequency output from the DVP mode deserializer will also be related to CLKIN when in DVP external clock mode. See Backward compatibility modes for operation with parallel output deserializers (SNLA270) for more information.
|REGISTER||REGISTER NAME||REGISTER DESCRIPTION|
|0X03||MODE_SEL||Used to override and verify strapped value, if necessary, and to configure for DVP with an external clock.|
|0X04||BC_MODE_SELECT||Allows DVP mode overwrites to RAW 10 or RAW 12.|
|0X10||DVP_CFG||Allows configuration of data in DVP mode. This includes data types like long, YUV, and specified types.|
|0X11||DVP_DT||Allows packets with certain data type regardless of RAW 10 or 12 mode if DVP_DT_MATCH_EN is asserted.|