SNLS696A April 2021 – May 2021 TSER953
When using the TSER953 in either synchronous or non-synchronous external clock modes, CLK_OUT is intended as a reference clock for the image sensor. CLK_OUT functionality is disabled when operating in non-synchronous internal clocking mode. The frequency of the external CLK_OUT is set by (see Equation 1 and Equation 2).
The PLL that generates CLK_OUT is a digital PLL, and as such, has very low jitter if the ratio N/M is an integer. If N/M is not an integer, then the jitter on the signal is approximately equal to HS_CLK_DIV/FC—so if it is not possible to have an integer ratio of N/M, it is best to select a smaller value for HS_CLK_DIV.
If a particular CLK_OUT frequency, such as 37.125 MHz, is required for a system, the designer can select the values M=9, N=0xF2, and HS_CLK_DIV=4 to achieve an output frequency of 37.190 MHz and a frequency error of 0.175% with an associate jitter of approximately 1 ns. Alternately, the designer could use M=1, N=0x1B, HS_CLK_DIV=4 for CLK_OUT = 37.037 MHz, and a frequency error of 0.24% for less jitter. A third alternative would be to use M=1, N=0x1B, and HS_CLK_DIV=4, but rather than using a 25.000-MHz reference clock frequency (REFCLK) for the deserializer in synchronous mode, use a frequency of 25.059 MHz. The 2x reference then fed to the TSER953 from the deserializer back channel will allow generating CLK_OUT = 37.124 MHz with both low jitter and a low frequency error.