7.5 Programming

The TUSB422 is controlled using I2C. The TUSB422 local I2C interface is available for reading/writing after T_{INT_N_LOW} after the device is powered up. The SCL and SDA terminals are used for I2C clock and I2C data respectively.

Figure 6. I2C Write With Data

The following procedure should be followed to write data to TUSB422 I²C registers (refer to Figure 6):

1. The master initiates a write operation by generating a start condition (S), followed by the TUSB422 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB422 acknowledges the address cycle.
3. The master presents the sub-address (I²C register within TUSB422) to be written, consisting of one byte of data, MSB-first.
4. The TUSB422 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I²C register.
6. The TUSB422 acknowledges the byte transfer
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TUSB422.
8. The master terminates the write operation by generating a stop condition (P).

Figure 7. I2C Read Without Repeated Start

The following procedure should be followed to read the TUSB422 I²C registers without a repeated Start (refer Figure 7).

1. The master initiates a read operation by generating a start condition (S), followed by the TUSB422 7-bit address and a zero-value “W/R” bit to indicate a read cycle.
2. The TUSB422 acknowledges the 7-bit address cycle.
3. Following the acknowledge the master continues sending clock.
4. The TUSB422 transmit the contents of the memory registers MSB-first starting at register 00h or last read sub-address+1. If a write to the I²C register occurred prior to the read, then the TUSB422 shall start at the sub-address specified in the write.
5. The TUSB422 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I²C master acknowledges reception of each data byte transfer.
6. If an ACK is received, the TUSB422 transmits the next byte of data as long as master provides the clock. If a NAK is received, the TUSB422 stops providing data and waits for a stop condition (P).
7. The master terminates the write operation by generating a stop condition (P).

Figure 8. I2C Read With Repeated Start

The following procedure should be followed to read the TUSB422 I²C registers with a repeated Start (refer Figure 8).

1. The master initiates a read operation by generating a start condition (S), followed by the TUSB422 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB422 acknowledges the 7-bit address cycle.
3. The master presents the sub-address (I²C register within TUSB422) to be written, consisting of one byte of data, MSB-first.
4. The TUSB422 acknowledges the sub-address cycle.
5. The master presents a repeated start condition (Sr).
6. The master initiates a read operation by generating a start condition (S), followed by the TUSB422 7-bit address and a one-value “W/R” bit to indicate a read cycle.
7. The TUSB422 acknowledges the 7-bit address cycle.
8. The TUSB422 transmit the contents of the memory registers MSB-first starting at the sub-address.
9. The TUSB422 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I²C master acknowledges reception of each data byte transfer.
10. If an ACK is received, the TUSB422 transmits the next byte of data as long as master provides the clock. If a NAK is received, the TUSB422 stops providing data and waits for a stop condition (P).
11. The master terminates the read operation by generating a stop condition (P).

Figure 9. I2C Write Without Data

The following procedure should be followed for setting a starting sub-address for I²C reads (refer to Figure 8).

1. The master initiates a write operation by generating a start condition (S), followed by the TUSB422 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB422 acknowledges the address cycle.
3. The master presents the sub-address (I²C register within TUSB422) to be written, consisting of one byte of data, MSB-first.
4. The TUSB422 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).

After initial power-up, if no sub-addressing is included for the read procedure (refer to Figure 8), then reads start at register offset 00h and continue byte by byte through the registers until the I²C master terminates the read operation. During a read operation, the TUSB422 auto-increments the I²C internal register address of the last byte transferred independent of whether or not an ACK was received from the I2C master.