SCES650K April   2006  – March 2025 TXB0104

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics (BQA/DYY)
    6. 5.6  Electrical Characteristics (Other Packages)
    7. 5.7  Timing Requirements: VCCA = 1.2 V
    8. 5.8  Timing Requirements: VCCA = 1.5 V ± 0.1 V
    9. 5.9  Timing Requirements: VCCA = 1.8 V ± 0.15 V
    10. 5.10 Timing Requirements: VCCA = 2.5 V ± 0.2 V
    11. 5.11 Timing Requirements: VCCA = 3.3 V ± 0.3 V
    12. 5.12 Switching Characteristics: VCCA = 1.2 V (BQA/DYY)
    13. 5.13 Switching Characteristics: VCCA = 1.2 V (Other Packages)
    14. 5.14 Switching Characteristics: VCCA = 1.5 V ± 0.1 V (BQA/DYY)
    15. 5.15 Switching Characteristics: VCCA = 1.5 V ± 0.1 V (Other Packages)
    16. 5.16 Switching Characteristics: VCCA = 1.8 V ± 0.15 V (BQA/DYY)
    17. 5.17 Switching Characteristics: VCCA = 1.8 V ± 0.15 V (Other Packages)
    18. 5.18 Switching Characteristics: VCCA = 2.5 V ± 0.2 V (BQA/DYY)
    19. 5.19 Switching Characteristics: VCCA = 2.5 V ± 0.2 V (Other Packages)
    20. 5.20 Switching Characteristics: VCCA = 3.3 V ± 0.3 V (BQA/DYY)
    21. 5.21 Switching Characteristics: VCCA = 3.3 V ± 0.3 V (Other Packages)
    22. 5.22 Operating Characteristics: VCCA = 1.2 V to 1.5 V, VCCB = 1.5 V to 1.8 V
    23. 5.23 Operating Characteristics: VCCA = 1.8 V to 3.3 V, VCCB = 1.8 V to 5 V
    24. 5.24 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Architecture
      2. 7.3.2 Input Driver Requirements
      3. 7.3.3 Output Load Considerations
      4. 7.3.4 Enable and Disable
      5. 7.3.5 Pullup or Pulldown Resistors on I/O Lines
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • RUT|12
  • NMN|12
  • YZT|12
  • PW|14
  • BQA|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Architecture

The TXB0104 device architecture (see Figure 7-1) does not require a direction-control signal to control the direction of data flow from A to B or from B to A. In a DC state, the output drivers of the device maintain a high or low, but are designed to be weak, so the output drivers can be overdriven by an external driver when data on the bus flows the opposite direction.

The output one-shots detect rising or falling edges on the A or B ports. During a rising edge, the one-shot turns on the PMOS transistors (T1, T3) for a short duration, which speeds up the low-to-high transition. Similarly, during a falling edge, the one-shot turns on the NMOS transistors (T2, T4) for a short duration, which speeds up the high-to-low transition. The typical output impedance during output transition is 70 Ω at VCCO = 1.2 V to 1.8 V, 50 Ω at VCCO = 1.8 V to 3.3 V, and 40 Ω at VCCO = 3.3 V to 5 V.

TXB0104 Architecture of TXB0104 Device I/O CellFigure 7-1 Architecture of TXB0104 Device I/O Cell