SLUSDV7B October 2019 – March 2021 UCC23313-Q1
Refer to the PDF data sheet for device specific package drawings
The external gate-driver resistors, RG(ON) and RG(OFF) are used to:
The output stage has a pull up structure consisting of a P-channel MOSFET and an N-channel MOSFET in parallel. The combined peak source current is 4.5 A Use Equation 1 to estimate the peak source current as an example.
In this example, the peak source current is approximately 1.7A as calculated in Equation 2.
Similarly, use Equation 3 to calculate the peak sink current.
In this example, the peak sink current is the minimum of 5.3A and Equation 4.
The diodes shown in series with each, RGON and RGOFF, in Figure 9-1 ensure the gate drive current flows through the intended path, respectively, during turn-on and turn-off. Note that the diode forward drop will reduce the voltage level at the gate of the power switch. To achieve rail-to-rail gate voltage levels, add a resistor from the VOUT pin to the power switch gate, with a resistance value approximately 20 times higher than RGON and RGOFF. For the examples described in this section, a good choice is 100 Ω to 200 Ω.
The estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot and undershoot. Therefore, TI strongly recommends that the gate-driver loop should be minimized. Conversely, the peak source and sink current is dominated by loop parasitics when the load capacitance (CISS) of the power transistor is very small (typically less than 1 nF) because the rising and falling time is too small and close to the parasitic ringing period.