During no-load operation, do allow sufficient margin for variations in VDD level to avoid the UVLO shutdown threshold. Also, at no-load, keep the average switching frequency, <fSW>, greater than 2 x fSW(min) to avoid a rise in output voltage.
Do clean flux residue and contaminants from the PCB after assembly. Uncontrolled leakage current from VS to GND causes the output voltage to increase, while leakage current from HV or VDD to VS causes output voltage to decrease.
If ceramic capacitors are used for VDD, do use quality parts with X7R or X5R dielectric rated 50 V or higher to minimize reduction of capacitance due to dc-bias voltage and temperature variation.
Do not use leaky components if less than 5-mW stand-by input power consumption is a design requirement.
Do not probe the VS node with an ordinary oscilloscope probe; the probe capacitance can alter the signal and disrupt regulation. Do observe VS indirectly by probing the auxiliary winding voltage at RS1 and scaling the waveform by the VS divider ratio.