SLUSBL5A February 2015 – June 2019 UCC28730
An internal high-voltage startup switch, connected to the bulk capacitor voltage (VBULK) through the HV pin, charges the VDD capacitor. This startup switch functions similarly to a current source providing typically 250 µA to charge the VDD capacitor. When VVDD reaches the 21-V UVLO turn-on threshold, the controller is enabled, the converter starts switching, and the startup switch turns off.
At initial turn-on, the output capacitor is often in a fully-discharged state. The first 4 switching-cycle current peaks are limited to IPP(min) to monitor for any initial input or output faults with limited power delivery. After these 4 cycles, if the sampled voltage at VS is less than 1.32 V, the controller operates in a special startup mode. In this mode, the primary-current-peak amplitude of each switching cycle is limited to approximately 0.67 x IPP(max) and DMAGCC increases from 0.432 to 0.650. These modifications to IPP(max) and DMAGCC during startup allow high-frequency charge-up of the output capacitor to avoid audible noise while the demagnetization voltage is low. Once the sampled VS voltage exceeds 1.36 V, DMAGCC is restored to 0.432 and the primary-current peak resumes as IPP(max). While the output capacitor charges, the converter operates in CC mode to maintain a constant output current until the output voltage enters regulation. Thereafter, the controller responds to conditions as dictated by the control law. The time to reach output regulation consists of the time the VDD capacitor charges to VVDD(on) plus the time the output capacitor charges.