SLUSBL5A February   2015  – June 2019 UCC28730


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Zero-Power Input Consumption at No-Load
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. VDD (Device Bias Voltage Supply)
        2. GND (Ground)
        3. HV (High Voltage Startup)
        4. DRV (Gate Drive)
        5. CBC (Cable Compensation)
        6. VS (Voltage Sense)
        7. CS (Current Sense)
      2. 7.3.2 Primary-Side Regulation (PSR)
      3. 7.3.3 Primary-Side Constant Voltage Regulation
      4. 7.3.4 Primary-Side Constant Current Regulation
      5. 7.3.5 Wake-Up Detection and Function
      6. 7.3.6 Valley-Switching and Valley-Skipping
      7. 7.3.7 Startup Operation
      8. 7.3.8 Fault Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Stand-By Power Estimate
        2. Input Bulk Capacitance and Minimum Bulk Voltage
        3. Transformer Turns Ratio, Inductance, Primary-Peak Current
        4. Transformer Parameter Verification
        5. Output Capacitance
        6. VDD Capacitance, CVDD
        7. VS Resistor Divider, Line Compensation, and Cable Compensation
        8. VS Wake-Up Detection
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Device Nomenclature
        1.  Capacitance Terms in Farads
        2.  Duty-Cycle Terms
        3.  Frequency Terms in Hertz
        4.  Current Terms in Amperes
        5.  Current and Voltage Scaling Terms
        6.  Transformer Terms
        7.  Power Terms in Watts
        8.  Resistance Terms in Ω
        9.  Timing Terms in Seconds
        10. DC Voltage Terms in Volts
        11. AC Voltage Terms in Volts
        12. Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Output Capacitance

With ordinary flyback converters, the output capacitance value is typically determined by the transient response requirement for a specific load step, ITRAN, sometimes from a no-load condition. For example, in some USB charger applications, there is requirement to maintain a transient minimum VO of 4.1 V with a load-step of 0 mA to 500 mA. Equation 20 below assumes that the switching frequency can be at the UCC28730 minimum of fSW(min).

Equation 20. UCC28730 qu20_lusbl5.gif

This results in a COUT value of over 17,000 µF, unless a substantial pre-load is used to raise the minimum switching frequency. However, the wake-up feature allows the use of a much smaller value for COUT because the wake-up response immediately cancels the Wait state and provides high-frequency power cycles to recover the output voltage from the load transient. The secondary-side voltage monitor UCC24650 provides the UCC28730 with a wake-up signal when it detects a -3% droop in output voltage.

Equation 21. UCC28730 qu21_lusbl5.gif


  • (dVOUT/dt) is the slope at which the UCC24650 must detect the VOUT droop. Use a slope factor of 3700 V/s or lower for this calculation.

The UCC28730 incorporates internal voltage-loop compensation circuits so that external compensation is not necessary, provided that the value of COUT is high enough. The following equation determines a minimum value of COUT necessary to maintain a phase margin of about 40 degrees over the full-load range. KCo is a dimensionless factor which has a value of 100.

Equation 22. UCC28730 qu22_lusbl5.gif

Another consideration for selecting the output capacitor(s) is the maximum ripple voltage requirement, VRIPPLE(max), which is reviewed based on the maximum output load, the secondary-peak current, and the equivalent series resistance (ESR) of the capacitor. The two major contributors to the output ripple voltage are the change in VOUT due to the charge and discharge of COUT between each switching cycle and the step in VOUT due to the ESR of COUT. TI recommends an initial allocation of 33% of VRIPPLE(max) to ESR, 33% to COUT, and the remaining 33% to account for additional low-level ripple from EMI-dithering, valley-hopping, sampling noise and other random contributors. In Equation 23, a margin of 50% is applied to the capacitor ESR requirement to allow for aging. In Equation 24, set ΔVCQ = 0.33 x VRIPPLE(max) to determine the minimum value of COUT with regard to ripple voltage limitation. If other allocations of the allowable ripple voltage are desired, these equations may be adjusted accordingly.

Equation 23. UCC28730 qu23_lusbl5.gif
Equation 24. UCC28730 qu23b_lusbl5.gif

Choose the largest value of the previous COUT calculations for the minimum output capacitance. If the value of COUT becomes excessive to meet a stringent ripple limitation, a C-L-C pi-filter arrangement can be considered to as an alternative to a simple capacitor-only filter. This arrangement is beyond the scope of this datasheet.