SLUSBL5A February 2015 – June 2019 UCC28730
PRODUCTION DATA.
With ordinary flyback converters, the output capacitance value is typically determined by the transient response requirement for a specific load step, I_{TRAN}, sometimes from a no-load condition. For example, in some USB charger applications, there is requirement to maintain a transient minimum V_{O} of 4.1 V with a load-step of 0 mA to 500 mA. Equation 20 below assumes that the switching frequency can be at the UCC28730 minimum of f_{SW(min)}.
This results in a C_{OUT} value of over 17,000 µF, unless a substantial pre-load is used to raise the minimum switching frequency. However, the wake-up feature allows the use of a much smaller value for C_{OUT} because the wake-up response immediately cancels the Wait state and provides high-frequency power cycles to recover the output voltage from the load transient. The secondary-side voltage monitor UCC24650 provides the UCC28730 with a wake-up signal when it detects a -3% droop in output voltage.
where
The UCC28730 incorporates internal voltage-loop compensation circuits so that external compensation is not necessary, provided that the value of C_{OUT} is high enough. The following equation determines a minimum value of C_{OUT} necessary to maintain a phase margin of about 40 degrees over the full-load range. K_{Co} is a dimensionless factor which has a value of 100.
Another consideration for selecting the output capacitor(s) is the maximum ripple voltage requirement, V_{RIPPLE(max)}, which is reviewed based on the maximum output load, the secondary-peak current, and the equivalent series resistance (ESR) of the capacitor. The two major contributors to the output ripple voltage are the change in V_{OUT} due to the charge and discharge of C_{OUT} between each switching cycle and the step in V_{OUT} due to the ESR of C_{OUT}. TI recommends an initial allocation of 33% of V_{RIPPLE(max)} to ESR, 33% to C_{OUT}, and the remaining 33% to account for additional low-level ripple from EMI-dithering, valley-hopping, sampling noise and other random contributors. In Equation 23, a margin of 50% is applied to the capacitor ESR requirement to allow for aging. In Equation 24, set ΔV_{CQ} = 0.33 x V_{RIPPLE(max)} to determine the minimum value of C_{OUT} with regard to ripple voltage limitation. If other allocations of the allowable ripple voltage are desired, these equations may be adjusted accordingly.
Choose the largest value of the previous C_{OUT} calculations for the minimum output capacitance. If the value of C_{OUT} becomes excessive to meet a stringent ripple limitation, a C-L-C pi-filter arrangement can be considered to as an alternative to a simple capacitor-only filter. This arrangement is beyond the scope of this datasheet.