SLUSBL5A February   2015  – June 2019 UCC28730

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Zero-Power Input Consumption at No-Load
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 VDD (Device Bias Voltage Supply)
        2. 7.3.1.2 GND (Ground)
        3. 7.3.1.3 HV (High Voltage Startup)
        4. 7.3.1.4 DRV (Gate Drive)
        5. 7.3.1.5 CBC (Cable Compensation)
        6. 7.3.1.6 VS (Voltage Sense)
        7. 7.3.1.7 CS (Current Sense)
      2. 7.3.2 Primary-Side Regulation (PSR)
      3. 7.3.3 Primary-Side Constant Voltage Regulation
      4. 7.3.4 Primary-Side Constant Current Regulation
      5. 7.3.5 Wake-Up Detection and Function
      6. 7.3.6 Valley-Switching and Valley-Skipping
      7. 7.3.7 Startup Operation
      8. 7.3.8 Fault Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stand-By Power Estimate
        2. 8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage
        3. 8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current
        4. 8.2.2.4 Transformer Parameter Verification
        5. 8.2.2.5 Output Capacitance
        6. 8.2.2.6 VDD Capacitance, CVDD
        7. 8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation
        8. 8.2.2.8 VS Wake-Up Detection
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1  Capacitance Terms in Farads
        2. 11.1.2.2  Duty-Cycle Terms
        3. 11.1.2.3  Frequency Terms in Hertz
        4. 11.1.2.4  Current Terms in Amperes
        5. 11.1.2.5  Current and Voltage Scaling Terms
        6. 11.1.2.6  Transformer Terms
        7. 11.1.2.7  Power Terms in Watts
        8. 11.1.2.8  Resistance Terms in Ω
        9. 11.1.2.9  Timing Terms in Seconds
        10. 11.1.2.10 DC Voltage Terms in Volts
        11. 11.1.2.11 AC Voltage Terms in Volts
        12. 11.1.2.12 Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range, VVDD = 25 V, HV = open, RCBC = open, TA = –40°C to 125°C, TJ = TA (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
HIGH-VOLTAGE START-UP
IHV Start-up current out of VDD VHV = 100 V, VVDD = 0 V, start state 100 250 500 µA
IHVLKG25 Leakage current into HV VHV = 400 V, run state, TJ = 25°C 0.01 0.5 µA
BIAS SUPPLY INPUT CURRENT
IRUN Supply current, run Run state, IDRV = 0 A 2.1 2.65 mA
IWAIT Supply current, wait Wait state, IDRV = 0 A, VVDD = 20 V 52 75 µA
ISTART Supply current, start Start state, IDRV = 0 A, VVDD = 18 V, IHV = 0 A 18 30 µA
IFAULT Supply current, fault Fault state, IDRV = 0 A 54 75 µA
UNDERVOLTAGE LOCKOUT
VVDD(on) VDD turn-on threshold VVDD low to high 17.5 21 23 V
VVDD(off) VDD turn-off threshold VVDD high to low 7.3 7.7 8.1 V
VS INPUT AND Wake-Up MONITOR
VVSR Regulating level(1) Measured at no-load condition,  TJ = 25°C 4 4.04 4.08 V
VVSNC Negative clamp level below GND IVSLS = –300 µA 190 250 325 mV
IVSB Input bias current VVS = 4 V –0.25 0 0.25 µA
VWU(high) Wake-up threshold at VS, high(2) VS pin rising 2 V
VWU(low) Wake-up threshold at VS, low VS pin rising 15 57 105 mV
CS INPUT
VCST(max) CS maximum threshold voltage(3) VVS = 3.7 V 710 740 770 mV
VCST(min) CS minimum threshold voltage VVS = 4.35 V 230 249 270 mV
KAM AM control ratio, VCST(max) / VCST(min) 2.75 2.99 3.2 V/V
VCCR Constant-current regulation factor 310 319 329 mV
KLC Line compensation current ratio, IVSLS / current out of CS pin IVSLS = –300 µA 24 25.3 28 A/A
DRIVER
IDRS DRV source current VDRV = 8 V, VVDD = 9 V 20 29 35 mA
RDRVLS DRV low-side drive resistance IDRV = 10 mA 6 12 Ω
VDRCL DRV clamp voltage VVDD = 35 V 13 14.5 16 V
RDRVSS DRV pull-down in start state 150 190 230 kΩ
PROTECTION
VOVP Over-voltage threshold(1) At VS input, TJ = 25°C 4.52 4.62 4.71 V
VOCP Over-current threshold At CS input 1.4 1.5 1.6 V
IVSL(run) VS line-sense run current Current out of VS pin increasing 190 225 275 µA
IVSL(stop) VS line-sense stop current Current out of VS pin decreasing 70 80 100 µA
KVSL VS line-sense ratio, IVSL(run) / IVSL(stop) 2.45 2.8 3.05 A/A
TJ(stop) Thermal shut-down temperature Internal junction temperature 165 °C
CABLE COMPENSATION
VCBC(max) Cable compensation output maximum voltage Voltage at CBC at full load 2.9 3.13 3.5 V
VCVS(min) Minimum compensation at VS VCBC = open, change in VS regulating level from no load to full load –50 –15 20 mV
VCVS(max) Maximum compensation at VS VCBC = 0 V, change in VS regulating level from no load to full load 275 325 375 mV
(1) The regulating level and OV threshold at VS decrease with increasing temperature by 1 mV/°C. This compensation over temperature is included to reduce the variances in power supply output regulation and over-voltage detection with respect to the external output rectifier.
(2) Designed for accuracy within ±10% of typical value.
(3) These threshold voltages represent average levels. This device automatically varies the current sense thresholds to improve EMI performance.