SWRS170L March 2014 – May 2025 WL1807MOD , WL1837MOD
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The interface includes four signals:
Flow control between the host and the device is byte-wise by hardware.
When the UART RX buffer of the device passes the flow-control threshold, the buffer sets the UART_RTS signal high to stop transmission from the host. When the UART_CTS signal is set high, the device stops transmitting on the interface. If HCI_CTS is set high in the middle of transmitting a byte, the device finishes transmitting the byte and stops the transmission.
Figure 7-10 shows the UART timing.
Figure 7-10 UART Timing DiagramTable 7-5 lists the UART timing characteristics.
| PARAMETER | CONDITION | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Baud rate | 37.5 | 4364 | Kbps | |||
| Baud rate accuracy per byte | Receive-transmit | –2.5% | 1.5% | |||
| Baud rate accuracy per bit | Receive-transmit | –12.5% | 12.5% | |||
| t3 | CTS low to TX_DATA on | 0.0 | 2.0 | µs | ||
| t4 | CTS high to TX_DATA off | Hardware flow control | 1.0 | bytes | ||
| t6 | CTS high pulse duration | 1.0 | Bit | |||
| t1 | RTS low to RX_DATA on | 0.0 | 2.0 | µs | ||
| t2 | RTS high to RX_DATA off | Interrupt set to 1/4 FIFO | 16.0 | bytes | ||
Figure 7-11 shows the UART data frame.
Figure 7-11 UART Data Frame