JAJSPW8E march   2011  – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions – LVDS Mode
    2.     Pin Functions – CMOS Mode
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS4246, ADS4245, ADS4242
    6. 7.6  Electrical Characteristics: ADS4226, ADS4225, ADS4222
    7. 7.7  Electrical Characteristics: General
    8. 7.8  Digital Characteristics
    9. 7.9  Timing Requirements: LVDS and CMOS Modes #GUID-C6C0701B-A11B-492F-BD6B-B774F5FE4665/SLAS6895399
    10. 7.10 Serial Interface Timing Characteristics #GUID-3852E7CE-C5B6-42F5-A56A-70AB1B981302/SBAS5097810
    11. 7.11 Reset Timing (Only When Serial Interface Is Used)
    12. 7.12 Typical Characteristics
      1. 7.12.1 ADS4246
      2. 7.12.2 ADS4245
      3. 7.12.3 ADS4242
      4. 7.12.4 ADS4226
      5. 7.12.5 ADS4225
      6. 7.12.6 ADS4222
      7. 7.12.7 General
      8. 7.12.8 Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Drive Circuit Requirements
        2. 8.3.1.2 Driving Circuit
      2. 8.3.2 Clock Input
      3. 8.3.3 Digital Functions
      4. 8.3.4 Gain for SFDR/SNR Trade-off
      5. 8.3.5 Offset Correction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down
        1. 8.4.1.1 Global Power-Down
        2. 8.4.1.2 Channel Standby
        3. 8.4.1.3 Input Clock Stop
    5. 8.5 Programming
      1. 8.5.1 47
      2. 8.5.2 Parallel Configuration Only
      3. 8.5.3 Serial Interface Configuration Only
      4. 8.5.4 Using Both Serial Interface and Parallel Controls
      5. 8.5.5 Parallel Configuration Details
      6. 8.5.6 Serial Interface Details
        1. 8.5.6.1 Register Initialization
        2. 8.5.6.2 Serial Register Readout
      7. 8.5.7 Digital Output Information
        1. 8.5.7.1 Output Interface
        2. 8.5.7.2 DDR LVDS Outputs
        3. 8.5.7.3 LVDS Buffer
        4. 8.5.7.4 Parallel CMOS Interface
        5. 8.5.7.5 CMOS Interface Power Dissipation
        6. 8.5.7.6 Multiplexed Mode of Operation
        7. 8.5.7.7 Output Data Format
    6. 8.6 Register Maps
      1. 8.6.1 64
      2. 8.6.2 Description Of Serial Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
        2. 9.2.2.2 Clock Driver
        3. 9.2.2.3 Digital Interface
        4. 9.2.2.4 SNR and Clock Jitter
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Sharing DRVDD and AVDD Supplies
      2. 9.3.2 Using DC/DC Power Supplies
      3. 9.3.3 Power Supply Bypassing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Grounding
        2. 9.4.1.2 Supply Decoupling
        3. 9.4.1.3 Exposed Pad
        4. 9.4.1.4 Routing Analog Inputs
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7 Electrical Characteristics: General

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, and –1 dBFS differential analog input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ANALOG INPUTS
Differential input voltage range0 dB gain2VPP
Differential input resistanceAt 200 MHz0.75kΩ
Differential input capacitanceAt 200 MHz3.7pF
Analog input bandwidthWith 50-Ω source impedance, and 50-Ω termination550MHz
Analog input common-mode currentPer input pin of each channel1.5µA/MSPS
Common-mode output voltageVCM0.95V
VCM output current capability4mA
DC ACCURACY
Offset error–152.515mV
Temperature coefficient of offset error0.003mV/°C
Gain error as a result of internal reference inaccuracy aloneEGREF–22%FS
Gain error of channel aloneEGCHANADS4246/ADS4226 (160 MSPS)±0.1–1%FS
ADS4245/ADS4225 (125 MSPS)±0.1
ADS4242/ADS4222 (65 MSPS)±0.1–1
Temperature coefficient of EGCHAN0.002Δ%/°C
POWER SUPPLY
IAVDD
Analog supply current		ADS4246/ADS4226 (160 MSPS)123150mA
ADS4245/ADS4225 (125 MSPS)105130
ADS4242/ADS4222 (65 MSPS)7385
IDRVDD
Output buffer supply current		LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHzADS4246/ADS4226 (160 MSPS)111135mA
ADS4245/ADS4225 (125 MSPS)99120
ADS4242/ADS4222 (65 MSPS)7895
IDRVDD
Output buffer supply current		CMOS interface, no load capacitance(1)
fIN = 2.5 MHz		ADS4246/ADS4226 (160 MSPS)61mA
ADS4245/ADS4225 (125 MSPS)49
ADS4242/ADS4222 (65 MSPS)28
Analog powerADS4246/ADS4226 (160 MSPS)222mW
ADS4245/ADS4225 (125 MSPS)189
ADS4242/ADS4222 (65 MSPS)133
Digital powerLVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHzADS4246/ADS4226 (160 MSPS)199mW
ADS4245/ADS4225 (125 MSPS)179
ADS4242/ADS4222 (65 MSPS)131
Digital powerCMOS interface, no load capacitance(1)
fIN = 2.5 MHz		ADS4246/ADS4226 (160 MSPS)109mW
ADS4245/ADS4225 (125 MSPS)88
ADS4242/ADS4222 (65 MSPS)50
Global power-down25mW
(1) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).