JAJSM94B June   2021  – June 2022 DAC12DL3200

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Power Consumption
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 2xRF Mode
      2. 7.3.2 DAC Output Interface
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-scale Current Adjustment
        3. 7.3.2.3 Example Analog Output Interfaces
      3. 7.3.3 LVDS Interface
        1. 7.3.3.1 MODE0: Two LVDS banks per channel
        2. 7.3.3.2 MODE1: One LVDS bank per channel
        3. 7.3.3.3 MODE2: Four LVDS banks, single channel mode
        4. 7.3.3.4 LVDS Interface Input Strobe
        5. 7.3.3.5 FIFO Operation
          1. 7.3.3.5.1 Using FIFO Delay Readback Values
          2. 7.3.3.5.2 FIFO Delay Handling
          3. 7.3.3.5.3 FIFO Delay and NCO Operation
          4. 7.3.3.5.4 FIFO Over/Under Flow Alarming
      4. 7.3.4 Multi-Device Synchronization (SYSREF+/-)
        1. 7.3.4.1 DACCLK Domain Synchronization
        2. 7.3.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 7.3.5 Alarms
    4. 7.4 Device Functional Modes
      1. 7.4.1 Direct Digital Synthesis (DDS) Mode
        1. 7.4.1.1 NCO Gain Scaling
        2. 7.4.1.2 NCO Phase Continuous Operation
        3. 7.4.1.3 Trigger Clock
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Operation
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 SPI Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure with LVDS Input
      2. 8.1.2 Startup Procedure With NCO Operation
      3. 8.1.3 Interface Test Pattern and Timing Verification
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.3 Interface Test Pattern and Timing Verification

The device provides the ability for the user to provide a repeating 8-sample sequence on the LVDS inputs and verify that the data can be properly received. It also provides debug facilities to help the user determine where the failures are occurring.

The test can be run both stop-on-fail (which allows the user to read the failing data frame to see what bits are failing and at what point in the pattern) or continue-on-fail (which allows the user to get a quick overview of which datalines are having problems).

Individual LVDS banks can be masked allowing the user to capture failures on selected banks.

  1. Start the DEVCLK

  2. Apply power

  3. Assert Reset

  4. De-assert Reset – Fuse ROM load will automatically begin

  5. Configure CH_CFG and DCM_EN according to the desired mode of operation. Only LVDS banks that are used in the selected mode will be tested.

  6. Start LVDS data into the part using the proper strobe period. Note that it is possible to use either the LSB strobe or the dedicated strobe pin. If using the LSB strobe, set SYNCB low (using either the pin or the register bit).

  7. Set DP_EN=1

  8. Synchronize the system

    1. If using LVDS Strobes for alignment:

      1. Set LVDS_STROBE_ALIGN=1

      2. Wait for LVDS_STROBE_DET=1

    2. If using SYSREF for alignment

      1. See SYSREF Windowing to enable and align synchronous SYSREF capturing.

      2. Set SYSREF_ALIGN_EN=1

      3. Wait for SYSREF_DET=1

      4. Set SYSREF_ALIGN_EN=0

  9. Check LVDS_STROBE_DET to ensure all the required LVDS strobes have been detected. Be sure to reset the bits before reading them. (Note that it is still possible to run the IOTEST if some strobes are not working. To do this, ensure that SYSREF is not being used so the FIFO does not corrupt the data. Then continue performing the test. The test will likely fail, but will provide visibility into what is occurring on the strobe line.)

  10. Configure FIFO_DLY (this may be done early but should be complete by here)

  11. Configure the IOTEST data patterns in IOTEST_PAT, and IOTEST_CONT.

  12. Set IOTEST_STRB_LOCK=1 (if desired).

  13. If using an LSB strobe and the pattern tests the LSb in data operation, set LSB_SYNC=0 and sync_n=1.

  14. Set IOTEST_EN=1

  15. Enable Transmission using txenable or TXEN_A/B.

  16. Start the test using IOTEST_TRIG.

  17. If IOTEST_CONT = 0, monitor IOTEST_RUN until the test stops and then inspect the results. If IOTEST_CONT = 1, monitor the faults using IOTEST_SUM or IOTEST_MISS* fields in registers IOTEST_STAT0 - IOTEST_STAT3.