There are many critical signals that require specific care during board design:

1. Analog output signals
2. CLK and SYSREF
3. LVDS data inputs at up to 1.6 Gbps
4. Power connections
5. Ground connections

Items 1 and 2 must be routed for excellent signal quality at high frequencies. Use the following general practices for these signals:

1. Route using loosely coupled 100-Ω differential traces. This routing minimizes impact of corners and length matching serpentines on pair impedance.
2. Provide adequate pair-to-pair spacing to minimize crosstalk.
3. Provide adequate ground plane pour spacing to minimize coupling with the high-speed traces.
4. Use smoothly radiused corners. Avoid 45- or 90-degree bends.
5. Incorporate ground plane cutouts at component landing pads to avoid impedance discontinuities at these locations. Cutout below the landing pads on one or multiple ground planes to achieve a pad size or stackup height that achieves the needed 50-Ω, single-ended impedance.
6. Avoid routing traces near irregularities in the reference ground planes. Irregularities include ground plane clearances associated with power and signal vias and through-hole component leads.
7. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias.
8. When high-speed signals must transition to another layer using vias, transition as far through the board as possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is not flexible, use back-drilled or buried, blind vias to eliminate stubs.

The LVDS data inputs must be routed with sufficient signal quality using the following general practices:

1. Route using tightly coupled 100-Ω differential traces to minimize the routing area and decrease crosstalk between adjacent data pairs.
2. Use smoothly radiused corners or 45-degree bends. Avoid 90-degree bends.
3. Avoid routing traces near irregularities in the reference ground planes. Irregularities include ground plane clearances associated with power and signal vias and through-hole component leads.
4. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias.
5. Data, clock, and strobe pairs must be sufficiently delay matched to provide adequate timing margin at the receiver. If routing on multiple layers, trace lengths must be compensated for the delay mismatch introduced by the effective dielectric constant of each layer.

In addition, TI recommends performing signal quality simulations of the critical signal traces before committing to fabrication. Perform insertion loss, return loss, and time domain reflectometry (TDR) evaluations. The power and ground connections for the device are also very important. These rules must be followed:

1. Provide low-resistance connection paths to all power and ground pins.
2. Use multiple power layers if necessary to access all pins.
3. Avoid narrow isolated paths that increase connection resistance.
4. Use a signal, ground, or power circuit board stackup to maximum coupling between the ground and power planes.