JAJSM94B June 2021 – June 2022 DAC12DL3200
PRODUCTION DATA
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
INPUT CLOCK (CLKIN+, CLKIN-) | ||||||
fCLK | Input clock frequency | 800 | 6400 | MHz | ||
LVDS INTERFACE | ||||||
fBIT | Dx[11:0]+/- DDR data rate | 1600 | Mbps | |||
UI | Dx[11:0]+/- DDR data unit interval | 625 | ps | |||
tSU(LVDS) | Setup time, Dx[11:0]+/– and DxSTR+/– valid to DxCLK+/– rising or falling edge | All LVDS buses | -375 | -240 | ps | |
tH(LVDS) | Hold time, DxCLK+/– rising or falling edge to Dx[11:0]+/– and DxSTR+/– transition | All LVDS buses | 495 | 565 | ps | |
fDCLK | DxCLK+/- DDR data clock frequency | 800 | MHz | |||
TRIGGER CLOCK | ||||||
FTRIGCLKMAX | Trigger clock maximum frequency | 100 | MHz | |||
tS_TRIGCLK | setup time for NCO_SEL[3:0] and NCOBANKSEL to TRIGCLK rising edge | 3.5 | ns | |||
tH_TRIGCLK | hold time for NCO_SEL[3:0] and NCOBANKSEL to TRIGCLK rising edge | -1.5 | ns | |||
SYSREF (SYSREF+, SYSREF-) | ||||||
tINV(SYSREF) | Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by SYSREF_POS status register(1) | 48 | ps | |||
tINV(TEMP) | Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward MSB of SYSREF_POS register | -0.12 | ps/°C | |||
tINV(VDDHAF) | Drift of invalid SYSREF capture region over VDDHAF supply voltage, positive number indicates a shift toward MSB of SYSREF_POS register | 0.33 | ps/mV | |||
tSTEP(SP) | Delay of SYSREF_SEL LSB | SYSREF_ZOOM = 0 | 22 | ps | ||
SYSREF_ZOOM = 1 | 9 | |||||
t(PH_SYS) | Minimum SYSREF± assertion duration after SYSREF± rising edge event | 4 | ns | |||
RESET | ||||||
tRESET | Minimum RESET pulse width | 25 | ns |