JAJSED2B August   2017  – January 2018 DAC5672A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     機能ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics: AC Characteristics
    8. 6.8  Electrical Characteristics: Digital Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Interfaces
      2. 7.3.2 Dual-Bus Data Interface and Timing
      3. 7.3.3 Single-Bus Interleaved Data Interface and Timing
    4. 7.4 Device Functional Modes
      1. 7.4.1 DAC Transfer Function
      2. 7.4.2 Analog Outputs
      3. 7.4.3 Output Configurations
      4. 7.4.4 Differential With Transformer
      5. 7.4.5 Single-Ended Configuration
      6. 7.4.6 Reference Operation
        1. 7.4.6.1 Internal Reference
        2. 7.4.6.2 External Reference
        3. 7.4.6.3 Gain Setting Option
        4. 7.4.6.4 Sleep Mode
    5. 7.5 Programming
      1. 7.5.1 Digital Inputs and Timing
        1. 7.5.1.1 Digital Inputs
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over TA, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode, (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DC SPECIFICATIONS
Resolution 14 Bits
DC ACCURACY (1)
INL Integral nonlinearity 1 LSB = IOUTFS / 214, TMIN to TMAX –4 ±1.1 4 LSB
DNL Differential nonlinearity –3 ±0.75 3 LSB
ANALOG OUTPUT
Offset error Midscale value ±0.03 %FSR
Offset mismatch Midscale value ±0.03 %FSR
Gain error With external reference ±0.25 %FSR
With internal reference ±0.25 %FSR
Minimum full-scale output current (2) 2 mA
Maximum full-scale output current (2) 20 mA
Gain mismatch With external reference –2 0.2 2 %FSR
With internal reference –2 0.2 2 %FSR
Output voltage compliance range (3) –1 1.25 V
RO Output resistance 300 kΩ
CO Output capacitance 5 pF
REFERENCE OUTPUT
Reference voltage 1.14 1.2 1.26 V
Reference output current (4) 100 nA
REFERENCE INPUT
VEXTIO Input voltage 0.1 1.25 V
RI Input resistance 1 MΩ
Small signal bandwidth 300 kHz
CI Input capacitance 100 pF
TEMPERATURE COEFFICIENTS
Offset drift 2 10 ppm of FSR/°C
Gain drift With external reference (DACA) 10 43 ppm of FSR/°C
With external reference (DACB) 20 80
With internal reference 40 160 ppm of FSR/°C
Reference voltage drift 20 ppm /°C
(1) Measured differently through 50 Ω to AGND.
(2) Nominal full-scale current (IOUTFS) equals 32 times the IBIAS current
(3) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the DAC5672A device. The upper limit of the output compliance is determined by the load resistors and ful-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
(4) Use an external buffer amplifier with high-impedance input to drive any external load.