JAJSED2B August   2017  – January 2018 DAC5672A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     機能ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics: AC Characteristics
    8. 6.8  Electrical Characteristics: Digital Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Interfaces
      2. 7.3.2 Dual-Bus Data Interface and Timing
      3. 7.3.3 Single-Bus Interleaved Data Interface and Timing
    4. 7.4 Device Functional Modes
      1. 7.4.1 DAC Transfer Function
      2. 7.4.2 Analog Outputs
      3. 7.4.3 Output Configurations
      4. 7.4.4 Differential With Transformer
      5. 7.4.5 Single-Ended Configuration
      6. 7.4.6 Reference Operation
        1. 7.4.6.1 Internal Reference
        2. 7.4.6.2 External Reference
        3. 7.4.6.3 Gain Setting Option
        4. 7.4.6.4 Sleep Mode
    5. 7.5 Programming
      1. 7.5.1 Digital Inputs and Timing
        1. 7.5.1.1 Digital Inputs
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.1 DAC Transfer Function

Each of the DACs in the DAC5672A has a set of complementary current outputs, IOUT1 and IOUT2. The full-scale output current, IOUTFS, is the summation of the two complementary output currents:

Equation 1. DAC5672A Equ_1_LAS440.gif

The individual output currents depend on the DAC code and can be expressed as:

Equation 2. DAC5672A Equ_2_LAS440.gif
Equation 3. DAC5672A Equ_3_LAS440.gif

where Code is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of the reference current IREF, which is determined by the reference voltage and the external setting resistor (RSET).

Equation 4. DAC5672A Equ_4_LAS440.gif

In most cases, the complementary outputs drive resistive loads or a terminated transformer. A signal voltage develops at each output according to:

Equation 5. DAC5672A Equ_5_LAS440.gif
Equation 6. DAC5672A Equ_6_LAS440.gif

The value of the load resistance is limited by the output compliance specification of the DAC5672A. To maintain specified linearity performance, the voltage for IOUT1 and IOUT2 must not exceed the maximum allowable compliance range.

The total differential output voltage is:

Equation 7. DAC5672A Equ_7_LAS440.gif
Equation 8. DAC5672A Equ_8_LAS440.gif