JAJSED2B August 2017 – January 2018 DAC5672A
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tsu | Input setup time | Dual bus mode | 1 | ns | ||
Single-bus interleaved mode | 0.5 | |||||
th | Input hold time | Dual bus mode | 1 | ns | ||
Single-bus interleaved mode | 0.5 | |||||
tLPH | Input clock pulse high time | Dual bus mode | 1 | ns | ||
Single-bus interleaved mode | ||||||
tLAT | Clock latency (WRT A/B to outputs) | Dual bus mode | 4 | 4 | clk | |
Single-bus interleaved mode | 4 | 4 | ||||
tPD | Propagation delay time | Dual bus mode | 1.5 | ns | ||
Single-bus interleaved mode | 1.5 |