JAJSHS6E August   2019  – August 2024 OPA810

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: 10 V
    6. 6.6  Electrical Characteristics: 24 V
    7. 6.7  Electrical Characteristics: 5 V
    8. 6.8  Typical Characteristics: VS = 10 V
    9. 6.9  Typical Characteristics: VS = 24 V
    10. 6.10 Typical Characteristics: VS = 5 V
    11. 6.11 Typical Characteristics: ±2.375-V to ±12-V Split Supply
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 OPA810 Architecture
      2. 7.3.2 ESD Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (±2.375 V to ±13.5 V)
      2. 7.4.2 Single-Supply Operation (4.75 V to 27 V)
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Amplifier Gain Configurations
      2. 8.1.2 Selection of Feedback Resistors
      3. 8.1.3 Noise Analysis and the Effect of Resistor Elements on Total Noise
    2. 8.2 Typical Applications
      1. 8.2.1 Transimpedance Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 High-Z Input Data Acquisition Front-End
      3. 8.2.3 Multichannel Sensor Interface
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 サード・パーティ製品に関する免責事項
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • DBV|5
  • DCK|5
サーマルパッド・メカニカル・データ

6.7 Electrical Characteristics: 5 V

at TA = 25°C, VS+ = 5 V, VS– = 0 V, common-mode voltage (VCM) = 1.25 V, and RL = 1 kΩ connected to 1.25 V(1) (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNITTest Level(2)
AC PERFORMANCE
SSBWSmall-signal bandwidthG = 1, Vo = 20 mVPP, RF = 0 Ω133MHzC
G = 1, Vo = 20 mVPP, RF= 0 Ω,
CL= 10 pF		135C
G = –1, Vo = 20 mVPP65C
LSBWLarge-signal bandwidthG = 2 Vo = 2 VPP36MHzC
GBWPGain-bandwidth product70MHzC
Bandwidth for 0.1-dB flatnessG = 2, Vo = 20 mVPP16MHzC
SRSlew rate (20%-80%)(3)G = 2, Vo = –1-V to 1-V step134V/µsC
G = 2, Vo = –2-V to 2-V step, 
VS = ±2.5 V		78C
Rise timeVo = 200-mV step4nsC
Fall timeVo = 200-mV step4nsC
Settling time to 0.1%G = 2, Vo = –2-V to 0-V step, 
VS = ±2.5 V		100nsC
Settling time to 0.001%G = 2, Vo = –2-V to 0-V step, 
VS = ±2.5 V		565nsC
Input overdrive recoveryG = 1, (VS– – 0.5 V) to (VS+ + 0.5 V) input, VS = ±2.5 V 76nsC
Output overdrive recoveryG = –1, (VS– – 0.5 V) to (VS+ + 0.5 V) input, VS = ±2.5 V 93nsC
HD2Second-order harmonic distortionf = 100 kHz, RL = 1 kΩ, Vo = 2 VPP–102dBcC
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP–81C
HD3Third-order harmonic distortionf = 100 kHz, RL = 1 kΩ, Vo = 2 VPP–114dBcC
f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP–92C
enInput-referred voltage noiseFlat-band, 1/f corner at 1.5 kHz6.3nV/√HzC
inInput-referred current noisef = 10 kHz5fA/√HzC
zOClosed-loop output impedancef = 100 kHz0.007ΩC
DC PERFORMANCE
AOLOpen-loop voltage gainf = dc, Vo = 1.25 V to 3.25 V104118dBA
VOSInput offset voltageSOIC package100550µVA
DBV and DCK packages100760
Input offset voltage driftTA = –40°C to +125°C2.510µV/°CB
Input bias current220pAA
Input offset current120pAA
CMRRCommon-mode rejection ratiof = dc, VCM = 0.75 V to 1.75 V, SOIC package7392dBA
TA = –40°C to +125°C, SOIC package73B
INPUT
Allowable input differential voltageSee Figure 6-54±5VC
Common-mode input impedanceIn closed-loop configuration12 || 2.5GΩ||pFC
Differential input capacitanceIn open-loop configuration0.5pFC
Most positive input voltageΔVOS < 5 mV(4)VS+ + 0.2VS+ + 0.3VA
Most negative input voltageΔVOS < 5 mV(4)VS- – 0.2VS- – 0.3VA
Most positive input voltage for main-JFET stage See Figure 6-41VS+ – 2.9VS+ – 2.5VC
OUTPUT
VOCRHOutput voltage range high RL = 667 ΩVS+ – 0.12VS+ – 0.09VA
TA = –40°C to +125°C, RLOAD = 667 ΩVS+ – 0.15B
VOCRLOutput voltage range low RL = 667 ΩVS–+ 0.06VS– + 0.11VA
TA = –40°C to +125°C, RL = 667 ΩVS– + 0.15B
IO(max)Linear output drive (sourcing and sinking) VO = 1.4 V, RL = 27.5 Ω, ΔVOS < 1 mV, VS+ = 3 V and VS– = –2 V5064mAA
ISCOutput short-circuit current96mAB
CLCapacitive load drive< 3-dB peaking, RS = 0 Ω10pFC
POWER SUPPLY
IQQuiescent current per channel3.153.74.5mAA
PSRRPower-supply rejection ratioΔVS = ±0.5 V(5), SOIC package78100dBA
TA = –40°C to +125°C, SOIC package78B
AUXILIARY CMOS INPUT STAGE
Gain-bandwidth product27MHzC
Input-referred voltage noise f = 1 MHz20nV/√HzC
Input offset voltageVCM = VS+ – 1.5 V, no load, SOIC package1.6mVA
Input bias currentVCM = VS+ – 1.5 V220pAA
(1) For ac specifications, VS+ = 3.5 V, VS– = –1.5 V, G = 2 V/V, RF = 1 kΩ, CL = 4.7 pF, VCM = 0 V (unless otherwise noted).
(2) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(3) Lower of the measured positive and negative slew rate.
(4) Change in input offset from the value when input is biased to 0 V.
(5) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to +PSRR and –PSRR.