JAJSDY1C June   2017  – March 2018 TPS25740B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 VBUS Capacitance
      2. 9.1.2 USB Data Communications
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  ENSRC
      2. 9.3.2  USB Type-C CC Logic (CC1, CC2)
      3. 9.3.3  USB PD BMC Transmission (CC1, CC2, VTX)
      4. 9.3.4  USB PD BMC Reception (CC1, CC2)
      5. 9.3.5  Discharging (DSCG, VPWR)
        1. 9.3.5.1 Discharging after a Fault (VPWR)
      6. 9.3.6  Configuring Voltage Capabilities (HIPWR)
      7. 9.3.7  Configuring Power Capabilities (PSEL, PCTRL, HIPWR)
      8. 9.3.8  Gate Driver (GDNG, GDNS)
      9. 9.3.9  Fault Monitoring and Protection
        1. 9.3.9.1 Over/Under Voltage (VBUS)
        2. 9.3.9.2 Over-Current Protection (ISNS, VBUS)
        3. 9.3.9.3 System Fault Input (GD, VPWR)
      10. 9.3.10 Voltage Control (CTL1, CTL2,CTL3)
      11. 9.3.11 Sink Attachment Indicator (DVDD)
      12. 9.3.12 Power Supplies (VAUX, VDD, VPWR, DVDD)
      13. 9.3.13 Grounds (AGND, GND)
      14. 9.3.14 Output Power Supply (DVDD)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Sleep Mode
      2. 9.4.2 Checking VBUS at Start Up
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 System-Level ESD Protection
      2. 10.1.2 Using ENSRC to Enable the Power Supply upon Sink Attachment
      3. 10.1.3 Use of GD Internal Clamp
      4. 10.1.4 Resistor Divider on GD for Programmable Start Up
      5. 10.1.5 Selection of the CTL1, CTL2, and CTL3 Resistors (R(FBL1), R(FBL2), and R(FBL3))
      6. 10.1.6 Voltage Transition Requirements
      7. 10.1.7 VBUS Slew Control using GDNG C(SLEW)
      8. 10.1.8 Tuning OCP using RF and CF
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Application, A/C Power Source (Wall Adapter)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Power Pin Bypass Capacitors
          2. 10.2.1.2.2 Non-Configurable Components
          3. 10.2.1.2.3 Configurable Components
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Typical Application, D/C Power Source
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Power Pin Bypass Capacitors
          2. 10.2.2.2.2 Non-Configurable Components
          3. 10.2.2.2.3 Configurable Components
        3. 10.2.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 D/C Power Source (Power Hub)
      2. 10.3.2 A/C Power Source (Wall Adapter)
      3. 10.3.3 Dual-Port A/C Power Source (Wall Adaptor)
      4. 10.3.4 D/C Power Source (Power Hub with 3.3 V Rail)
  11. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  12. 12Layout
    1. 12.1 Port Current Kelvin Sensing
    2. 12.2 Layout Guidelines
      1. 12.2.1 Power Pin Bypass Capacitors
      2. 12.2.2 Supporting Components
    3. 12.3 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.5.1 Discharging after a Fault (VPWR)

There are two types of faults that cause the TPS25740B to begin a full discharge of VBUS: Slow-shutdown faults and fast-shutdown faults. When a slow-shutdown fault occurs, the device does not disable GDNG until after VBUS is measured below V(SOVP) for a 5V contract. When a fast-shutdown fault occurs, the device disables GDNG immediately and then discharges the connector side of the power-path. In both cases, the bleed discharge is applied to the DSCG pin and I(SUPP) is drawn from the VPWR

Slow-shutdown faults that do not include transmitting a hard reset:

  • Receiving a Hard Reset signal (25 ms < tShutdownDelay < 35 ms)
  • Cable is unplugged (tShutdownDelay < 20 µs)

Slow-shutdown faults that include transmitting hard reset (25 ms < tShutdownDelay < 35 ms)

  • TJ exceeds TJ1 (an overtemperature event)
  • Low voltage alarm occurring outside of a voltage transition
  • High voltage alarm occurring outside of a voltage transition (but not high enough to cause OVP)
  • Receiving an unexpected PD message during a voltage transition
  • Failure of power supply to transition voltages within required time of 600 ms (tPSTransition (refer to USB PD in ドキュメントのサポート).
  • A Soft Reset USB PD message is not acknowledged or Accepted (refer to USB PD in ドキュメントのサポート).
  • A Request USB PD message is not received in the required time (refer to USB PD in ドキュメントのサポート).
  • Failure to discharge down to 0.725 V after a fault of any kind.

Fast-shutdown faults (hard reset always sent):

  • Fast OVP event occurring at any time.
  • OCP event occurring at any time starting from the transmission of the first USB PD message.
    • VBUS falling below V(VBUS_FTH) is treated as an OCP event.
  • GD falling edge

The DSCG pin is used to discharge the supply line after a slow-shutdown fault occurs. Figure 31 illustrates the signals involved. Depending on the specific slow-shutdown fault the time tShutdownDelay in Figure 31 is different as indicated in the list above. If the slow-shutdown fault triggers a hard reset, it is sent at the beginning of the tShutdownDelay period. However, the device behavior after the time tShutdownDelay is the same for all slow-shutdown faults. After the tShutdownDelay period, the device sets CTL1, CTL2, and CTL3 to select 5 V from the power supply and puts the DSCG pin into its ON state (Full Discharge). This discharging continues until the voltage on the VBUS pin reaches V(SOVP) for a 5-V contract. The device then disables GDNG and again puts the DSCG pin into its ON state. This discharging state lasts until the voltage on VBUS reaches 0.725 V (nominal). If the discharge does not complete within 650 ms, then the device sends a Hard Reset signal and the process repeats. In Figure 31, the times labeled as t15→5 and t5→0 can vary, they depend on the size of the capacitance to be discharged and the size of the external resistor between the DSCG pin and VBUS. The time labeled as tS is a function of how quickly the NFET opens.

TPS25740B Slow_Shutdown_slvsdr6.gifFigure 31. Illustration of Slow-Shutdown VBUS Discharge

Figure 32 illustrates a similar discharge procedure for fast-shutdown faults. The main difference from Figure 31 is that the NFET is opened immediately. It is assumed for the purposes of this illustration that the power supply output capacitance (that is, C(SOURCE) in the reference schematics shown in Figure 21 and Figure 22) is not discharged by the power supply itself, but the VPWR pin is bleeding current from that capacitance. The VPWR pin then draws I(SUPP) after GDNG disables the external NFET. So, as shown in the figure, the VPWR voltage discharges slowly, while the VBUS pin is discharged once the full discharge is enabled. If the voltage on the VPWR pin takes longer than t15→5 + t5→0 + 0.765s to discharge below V(FOVP), then it causes an OVP event and the process repeats.

TPS25740B Fast_Shutdown_slvsdr6.gifFigure 32. Illustration of Fast-Shutdown Discharge

If the discharge does not complete successfully it is treated as a slow-shutdown fault, and the device repeats the discharge procedure until it does complete successfully. Once the discharge completes successfully as described above (that is, VBUS on connector is below 0.725 V), the device waits for 0.765 s (nominal) before trying to source VBUS again.