JAJSMF3A May   2022  – September 2022 TPS25985

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Logic Interface
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Protection
      2. 8.3.2  Insertion Delay
      3. 8.3.3  Overvoltage Protection
      4. 8.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 8.3.4.1.1 Start-Up Time Out
        2. 8.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 8.3.4.3 Active Current Limiting During Start-Up
        4. 8.3.4.4 Short-Circuit Protection
      5. 8.3.5  Analog Load Current Monitor (IMON)
      6. 8.3.6  Mode Selection (MODE)
      7. 8.3.7  Parallel Device Synchronization (SWEN)
      8. 8.3.8  Stacking Multiple eFuses for Unlimited Scalability
        1. 8.3.8.1 Current Balancing During Start-Up
      9. 8.3.9  Analog Junction Temperature Monitor (TEMP)
      10. 8.3.10 Overtemperature Protection
      11. 8.3.11 Fault Response and Indication (FLT)
      12. 8.3.12 Power Good Indication (PG)
      13. 8.3.13 Output Discharge
      14. 8.3.14 General Purpose Comparator
      15. 8.3.15 FET Health Monitoring
      16. 8.3.16 Single Point Failure Mitigation
        1. 8.3.16.1 IMON Pin Single Point Failure
        2. 8.3.16.2 ILIM Pin Single Point Failure
        3. 8.3.16.3 IREF Pin Single Point Failure
        4. 8.3.16.4 ITIMER Pin Single Point Failure
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Standalone Operation
      2. 9.1.2 Multiple Devices, Parallel Connection
    2. 9.2 Typical Application: 12-V, 3.6-kW Power Path Protection in Datacenter Servers
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Performance Plots
    3. 9.3 Multiple eFuses, Parallel Connection with PMBus
    4. 9.4 Digital Telemetry Using External Microcontroller
    5. 9.5 What to Do and What Not to Do
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.6 Mode Selection (MODE)

This pin can be used to configure the TPS25985x as a primary device in a chain along with other TPS25985x eFuses, designated as secondary devices. This feature allows some of the TPS25985x pin functions to be changed to aid the primary + secondary parallel connection.

This pin is sampled at power up. Leaving the pin open configures it as a primary or standalone device. Connecting this pin to GND configures it as a secondary device.

The following functions are disabled in secondary mode and the device relies on the primary device to provide this functionality:

  1. IREF internal current source

  2. DVDT internal current source

  3. Overcurrent detection in steady-state for circuit-breaker response

  4. PG de-assertion (pulldown) after reaching steady-state

  5. Latch-off after fault

In secondary mode, the following functions are still active:

  1. Overtemperature protection

  2. Start-up current limit based on ILIM

  3. Active current sharing during inrush as well as steady-state

  4. Analog current monitor (IMON) in steady state

  5. Steady-state overcurrent detection based on IMON. This is indicated by pulling ITIMER pin low internally, but does not trigger circuit-breaker action on ITIMER expiry. Rather, it relies on the primary device to start its own ITIMER and then trigger the circuit-breaker action for the whole chain by pulling SWEN low after the ITIMER expiry. However, the secondary devices use an internal overcurrent timer as a backup in case the primary device fails to initiate circuit-breaker action for an extended period of time. Refer to Single Point Failure Mitigation section for details.

  6. Each device still has individual scalable and fixed fast-trip thresholds to protect itself. The individual short-circuit protection threshold is set to maximum, that is 2.25 × IOCP (steady-state) or 2 × ILIM (start-up) in secondary mode so that the primary device can lower it further for the whole system.

  7. Individual OVP is set to maximum in secondary device so that the primary can lower it further for the whole system.

  8. FLT assertion based on individual device fault detection (except circuit-breaker).

  9. PG de-assertion control during inrush and assertion control after device reaches steady state. However, after that in steady state, the secondary device no longer controls the de-assertion of the PG in case of faults.

  10. SWEN assertion or de-assertion based on internal events as well as FET ON and OFF control based on SWEN pin status.

In secondary mode, the device behavior during short-circuit and fast-trip is also altered. More details are available in the Short-Circuit Protection section.