JAJSMF3A May   2022  – September 2022 TPS25985

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Logic Interface
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Protection
      2. 8.3.2  Insertion Delay
      3. 8.3.3  Overvoltage Protection
      4. 8.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 8.3.4.1.1 Start-Up Time Out
        2. 8.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 8.3.4.3 Active Current Limiting During Start-Up
        4. 8.3.4.4 Short-Circuit Protection
      5. 8.3.5  Analog Load Current Monitor (IMON)
      6. 8.3.6  Mode Selection (MODE)
      7. 8.3.7  Parallel Device Synchronization (SWEN)
      8. 8.3.8  Stacking Multiple eFuses for Unlimited Scalability
        1. 8.3.8.1 Current Balancing During Start-Up
      9. 8.3.9  Analog Junction Temperature Monitor (TEMP)
      10. 8.3.10 Overtemperature Protection
      11. 8.3.11 Fault Response and Indication (FLT)
      12. 8.3.12 Power Good Indication (PG)
      13. 8.3.13 Output Discharge
      14. 8.3.14 General Purpose Comparator
      15. 8.3.15 FET Health Monitoring
      16. 8.3.16 Single Point Failure Mitigation
        1. 8.3.16.1 IMON Pin Single Point Failure
        2. 8.3.16.2 ILIM Pin Single Point Failure
        3. 8.3.16.3 IREF Pin Single Point Failure
        4. 8.3.16.4 ITIMER Pin Single Point Failure
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Single Device, Standalone Operation
      2. 9.1.2 Multiple Devices, Parallel Connection
    2. 9.2 Typical Application: 12-V, 3.6-kW Power Path Protection in Datacenter Servers
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Performance Plots
    3. 9.3 Multiple eFuses, Parallel Connection with PMBus
    4. 9.4 Digital Telemetry Using External Microcontroller
    5. 9.5 What to Do and What Not to Do
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.1 Layout Guidelines

  • For all applications, TI recommends a ceramic decoupling capacitor of 0.1 μF or greater between the IN terminal and GND terminal.

  • For all applications, TI recommends a ceramic decoupling capacitor of 2.2 μF or greater between the OUT terminal and GND terminal.

  • The optimal placement of the decoupling capacitor is closest to the IN and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN terminal, and the GND terminal of the IC. See Figure below for a PCB layout example.

  • High current-carrying power-path connections must be as short as possible and must be sized to carry at least twice the full-load current.

  • The GND terminal must be tied to the PCB ground plane at the terminal of the IC. The PCB ground must be a copper plane or island on the board.

  • The IN and OUT pins are used for Heat Dissipation. Connect to as much copper area as possible with thermal vias.

  • Locate the following support components close to their connection pins:

    • RILIM

    • RIMON

    • CIMON

    • RIREF

    • CIREF

    • CdVdT

    • CITIMER

    • CIN

    • COUT

    • CVDD

    • Resistors for the EN/UVLO pin

  • Connect the other end of the component to the GND pin of the device with shortest trace length. The trace routing for the CIN, COUT, CVDD, RIREF, CIREF, RILIM, RIMON, CIMON, CITIMER and CdVdt components to the device must be as short as possible to reduce parasitic effects on the current limit, overcurrent blanking interval and soft-start timing. These traces must not have any coupling to switching signals on the board.

  • Because the IMON, ILIM, IREF and ITIMER pins directly control the overcurrent protection behavior of the device, the PCB routing of these nodes must be kept away from any noisy (switching) signals.

  • TI recommends to keep the parasitic loading on SWEN pin to a minimum to avoid synchronization issues.

  • Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect. These protection devices must be routed with short traces to reduce inductance. For example, TI recommends a protection Schottky diode to address negative transients due to switching of inductive loads, and it must be physically close to the OUT pins.