JAJSGA2F September   2018  – June 2021 TPS2663


  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Hot Plug-In and In-Rush Current Control
        1. Thermal Regulation Loop
      2. 9.3.2  PGOOD and PGTH
        1. PGTH as VOUT Sensing Input
      3. 9.3.3  Undervoltage Lockout (UVLO)
      4. 9.3.4  Overvoltage Protection (OVP)
      5. 9.3.5  Input Reverse Polarity Protection (B_GATE, DRV)
      6. 9.3.6  Reverse Current Protection
      7. 9.3.7  Overload and Short Circuit Protection
        1. Overload Protection
          1. Active Current Limiting at 1x IOL, (TPS26630 and TPS26632 Only)
          2. Active Current Limiting with 2x IOL Pulse Current Support, (TPS26631, TPS26633, TPS26635 and TPS26636 Only)
        2. Short Circuit Protection
          1. Start-Up With Short-Circuit On Output
      8. 9.3.8  Output Power Limiting, PLIM (TPS26632, TPS26633, TPS26635 and TPS26636 Only)
      9. 9.3.9  Current Monitoring Output (IMON)
      10. 9.3.10 FAULT Response ( FLT)
      11. 9.3.11 IN_SYS, IN, OUT and GND Pins
      12. 9.3.12 Thermal Shutdown
      13. 9.3.13 Low Current Shutdown Control (SHDN)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Power Path Protection in a PLC System
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. Programming the Current-Limit Threshold—R(ILIM) Selection
        2. Undervoltage Lockout and Overvoltage Set Point
        3. Output Buffer Capacitor – COUT
        4. PGTH Set Point
        5. Setting Output Voltage Ramp Time—(tdVdT)
          1. Support Component Selections— RPGOOD and C(IN)
        6. Selecting Q1, Q2 and TVS Clamp for Surge Protection
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Simple 24-V Power Supply Path Protection
      2. 10.3.2 Priority Power MUX Operation
      3. 10.3.3 Input Protection for a Compact 24-V Auxiliary Power Supply for Servo Drives
    4. 10.4 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information


  • RGE|24
  • PWP|20

Overvoltage Protection (OVP)

The TPS2663x devices incorporate circuitry to protect the system during overvoltage conditions. The TPS26630 and TPS26631 feature an accurate ± 2% adjustable overvoltage cut off functionality. A voltage more than V(OVPR) on OVP pin turns off the internal FET and protects the downstream load. To program the OVP threshold externally, connect a resistor divider from IN_SYS supply to OVP terminal to GND as shown in the Simplified Schematic.

The TPS26630 and TPS26631 also feature a factory set 34.3-V input overvoltage cut off V(IN_SYS_OVP) threshold with a 440 mV hysteresis. This feature can be enabled by connecting the OVP terminal directly to the GND terminal. The TPS26632, TPS26633 and TPS26636 feature an internally fixed 35-V maximum overvoltage clamp V(OVC) functionality. The TPS26632 and TPS26633 clamps the output voltage to V(OVC), when the input voltage exceeds 35 V. TPS26635 features a fixed 39-V maximum overvoltage clamp level. During the output voltage clamp operation, the power dissipation in the internal MOSFET is PD = (V(IN_SYS) – V(OVC)) × I(OUT). Excess power dissipation for a prolonged period can increase the device temperature. To avoid this, the internal FET is operated in overvoltage clamp for a maximum duration of tOVC(dly), 162 msec (typical). After this duration, the internal FET is turned OFF and the subsequent operation of the device depends on the MODE configuration (Auto-Retry or latch OFF) setting as shown in Table 9-1.

Figure 8-1 shows the turn ON behavior when OVP pin voltage falls below V(OVPF) threshold.

Figure 9-3 illustrates the overvoltage cut-off functionality and Figure 9-4 illustrates the overvoltage clamp functionality. FLT is asserted after a delay of 617 µs (typical) after entering in overvoltage clamp mode and remains asserted until the overvoltage fault is removed.

TPS26630 and TPS26631
Figure 9-3 Overvoltage Cut-off Response at 33-V Level
TPS26635 RLOAD = 30 Ω, FLT connected to VOUT
Figure 9-4 Overvoltage Clamp Response with TPS26635