JAJSGA2F September   2018  – June 2021

PRODUCTION DATA

1. 特長
2. アプリケーション
3. 概要
4. Revision History
5. Device Comparison Table
6. Pin Configuration and Functions
7. Specifications
8. Parameter Measurement Information
9. Detailed Description
1. 9.1 Overview
2. 9.2 Functional Block Diagram
3. 9.3 Feature Description
4. 9.4 Device Functional Modes
10. 10Application and Implementation
1. 10.1 Application Information
2. 10.2 Typical Application: Power Path Protection in a PLC System
1. 10.2.1 Design Requirements
2. 10.2.2 Detailed Design Procedure
3. 10.2.3 Application Curves
3. 10.3 System Examples
4. 10.4 Do's and Don'ts
11. 11Power Supply Recommendations
12. 12Layout
13. 13Device and Documentation Support
14. 14Mechanical, Packaging, and Orderable Information

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

• RGE|24
• PWP|20
• PWP|20
• RGE|24

### 9.3.6 Reverse Current Protection

The device monitors V(IN_SYS) and V(OUT) to provide true reverse current blocking when a reverse condition or input power failure condition is detected. The reverse comparator turns OFF the external blocking FET Q1 quickly as soon as V(IN_SYS) – V(OUT) falls below –1 V. The total time taken to turn OFF the FET Q1 in this condition is tRCB(fast_dly) + t(Driver). The delay due to the driver stage t(Driver) can be calculated using Equation 4.

Equation 4.

where

• RDSON(Q2) is the on resistance of the fast pull down switch Q2
• Ciss(Q1) is the input capacitance of the blocking FET Q1
• VGTH(Q1) is the GATE threshold voltage of the blocking FET Q1
• VBGATE = 10.2 V (typical)

In a typical system design, t(Driver) is generally 10% to 20% of tRCB(fast_dly) of 120 nsec (typical).

Figure 9-8 and Figure 9-9 illustrates the behavior of the system during input hot short circuit condition. The blocking FET Q1 is turned ON within 1.6 ms (typical) once the differential forward voltage V(IN_SYS) – V(OUT) exceeds 67 mV (typical).

Figure 9-8 Input Hot Short Functionality at 24-V Supply
Figure 9-9 Input Hot-Short: Fast Trip Response (Zoomed)

The reverse comparator architecture has a supply line noise immunity resulting in a robust performance in noisy environments. This is achieved by controlling the turn OFF time of the internal FET based on the over-drive differential voltage V(IN_SYS) – V(OUT) over V(REVTH). Higher the over-drive, faster the turn OFF time, tRCB(dly).