JAJSGA2F September 2018 – June 2021 TPS2663
The device monitors V(IN_SYS) and V(OUT) to provide true reverse current blocking when a reverse condition or input power failure condition is detected. The reverse comparator turns OFF the external blocking FET Q1 quickly as soon as V(IN_SYS) – V(OUT) falls below –1 V. The total time taken to turn OFF the FET Q1 in this condition is tRCB(fast_dly) + t(Driver). The delay due to the driver stage t(Driver) can be calculated using Equation 4.
In a typical system design, t(Driver) is generally 10% to 20% of tRCB(fast_dly) of 120 nsec (typical).
Figure 9-8 and Figure 9-9 illustrates the behavior of the system during input hot short circuit condition. The blocking FET Q1 is turned ON within 1.6 ms (typical) once the differential forward voltage V(IN_SYS) – V(OUT) exceeds 67 mV (typical).
The reverse comparator architecture has a supply line noise immunity resulting in a robust performance in noisy environments. This is achieved by controlling the turn OFF time of the internal FET based on the over-drive differential voltage V(IN_SYS) – V(OUT) over V(REVTH). Higher the over-drive, faster the turn OFF time, tRCB(dly).