JAJSGA2F September 2018 – June 2021 TPS2663
During a transient output short circuit event, the current through the device increases rapidly. As the current-limit amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip comparator. The fast-trip comparator architecture is designed for fast turn OFF tFASTTRIP(dly) = 1 µs (typical) with I(SCP) = 45 A of the internal FET during an output short circuit event. The fast-trip threshold is internally set to I(FASTTRIP). The fasttrip circuit holds the internal FET off for only a few microseconds, after which the device turns back on slowly, allowing the current-limit loop to regulate the output current to I(OL). Then the device functions similar to the overload condition. Figure 8-14 illustrates output hot-short performance of the device.
|VIN_SYS = 24 V||RILIM = 9.09 kΩ|
The fast-trip comparator architecture has a supply line noise immunity resulting in a robust performance in noisy environments. This is achieved by controlling the turn OFF time of the internal FET based on the overcurrent level, I(FASTTRIP) through the device. Higher the overcurrent, faster the turn OFF time, tFASTTRIP(dly). At overload current level in the range of IFASTTRIP < IOUT < ISCP the fast-trip comparator response is 3.2 μs (typical).