JAJSGA2F September 2018 – June 2021 TPS2663
The devices use PGTH as the output (Load) voltage monitor input and to set the down stream loads UVLO threshold. To set the input PGTH threshold, connect a resistor divider network from VOUT to PGTH terminal to GND as shown in the Simplified Schematic. During a system fault recovery (example: OVP high to low or UVLO low to high) when the internal FET gate control is enabled, the device samples the PGTH information and decides whether to turn ON the FET with fast slew rate or dVdT mode based on the sampled V(PGTH) information.
Figure 8-1 shows the turn ON behavior based on V(PGTH) information. During the fault recovery instance if the V(PGTH) level is above(PGTHF) then the internal FET turns ON within a delay of tOVP(dly_fast) with fast slew rate (ignores the capacitance connected at dVdT pin) with thermal regulation loop enabled for a duration of tCL_PLIM(dly). Maximum current through the device during this operation is limited at I(OL) in TPS26630 and TPS26632 devices and at 2 x I(OL) in TPS26631, TPS26633, TPS26635 and TPS26636 devices for a maximum duration of tCB(dly). During the fault recovery instance if the V(PGTH) level is below V(PGTHF) then the device turns ON the internal FET in dVdT mode and the slew rate will depend on the dVdT capacitor value and maximum current through the devices is limited at I(OL). This way the device distinguishes between real system faults and system transients and the turn ON delay is controlled accordingly. This scheme ensures fast recovery during system tests like voltage interruption and brown-out tests, EMC testing like Electrical Fast Transients (IEC61000-4-4) and Surge (IEC61000-4-5). The fast turn ON during transient recovery feature can be disabled by connecting PGTH to GND. In this case, PGOOD will be pulled low.