JAJSKH0 データシート

JAJSKH0C April 2023 – February 2024 TPS274C65

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RHA|40
- MPQF135D

サーマルパッド・メカニカル・データ

RHA|40
- QFND047R

発注情報

8.6 TPS274C65 Registers

Table 8-12 lists the memory-mapped registers for the TPS274C65 registers. All register offset addresses not listed in Table 8-12 should be considered as reserved locations and the register contents should not be modified.

Table 8-12 TPS274C65 Registers

Offset	Acronym	Register Name	Section
0h	FAULT_TYPE_STAT	Fault Type Register	Section 8.6.1
1h	FAULT_CH_STAT	Faulted channel register	Section 8.6.2
2h	FAULT_GLOBAL_TYPE	Global fault type register	Section 8.6.3
3h	SHRT_VS_CH_STAT	Short_to VS Faulted Channel Register	Section 8.6.4
4h	WB_OFF_CH_STAT	Off-state Wire-break faulted channel register	Section 8.6.5
5h	WB_ON_CH_STAT	On-state Wire-break faulted channel register	Section 8.6.6
6h	ILIMIT_CH_STAT	Current Limit faulted channel register	Section 8.6.7
7h	THERMAL_SD_CH_STAT	Thermal Shutdown faulted channel register	Section 8.6.8
8h	THERMAL_WRN_CH_STAT	Thermal warning threshold faulted channel register	Section 8.6.9
9h	RVRS_BLK_CH_STAT	Reverse Current flow (blocked) faulted channel register	Section 8.6.10
Bh	ADC_RESULT_CH1_I	ADC conversion result ISNS CH1	Section 8.6.11
Ch	ADC_RESULT_CH1_I_LSB	ADC conversion result ISNS CH1 LSBs	Section 8.6.12
Dh	ADC_RESULT_CH2_I	ADC conversion result ISNS CH2	Section 8.6.13
Eh	ADC_RESULT_CH2_I_LSB	ADC conversion result ISNS CH2 LSBs	Section 8.6.14
Fh	ADC_RESULT_CH3_I	ADC conversion result ISNS CH3	Section 8.6.15
10h	ADC_RESULT_CH3_I_LSB	ADC conversion result ISNS CH3 LSBs	Section 8.6.16
11h	ADC_RESULT_CH4_I	ADC conversion result ISNS CH4	Section 8.6.17
12h	ADC_RESULT_CH4_I_LSB	ADC conversion result ISNS CH4 LSBs	Section 8.6.18
13h	ADC_RESULT_CH1_T	ADC conversion result TSNS CH1	Section 8.6.19
14h	ADC_RESULT_CH2_T	ADC conversion result TSNS CH2	Section 8.6.20
15h	ADC_RESULT_CH3_T	ADC conversion result TSNS CH3	Section 8.6.21
16h	ADC_RESULT_CH4_T	ADC conversion result TSNS CH4	Section 8.6.22
17h	ADC_RESULT_CH1_V	ADC conversion result VSNS CH1	Section 8.6.23
18h	ADC_RESULT_CH2_V	ADC conversion result VSNS CH2	Section 8.6.24
19h	ADC_RESULT_CH3_V	ADC conversion result VSNS CH3	Section 8.6.25
1Ah	ADC_RESULT_CH4_V	ADC conversion result VSNS CH4	Section 8.6.26
1Bh	ADC_RESULT_VS	ADC conversion result VS	Section 8.6.27
1Ch	ADC_RESULT_VS_LSB	ADC conversion result VS	Section 8.6.28
1Dh	SW_STATE	Switch state per channel register	Section 8.6.29
1Eh	LED1_4_CTL	LED1-LED4 Control	Section 8.6.30
1Fh	LED_5_8_CTL	LED5-LED8 Control	Section 8.6.31
20h	FS_SW_STATE	SPI/WD error state per channel register	Section 8.6.32
21h	DEV_CONFIG1	Device Configuration Register #1	Section 8.6.33
22h	DEV_CONFIG2	Device Configuration Register #2	Section 8.6.34
23h	DEV_CONFIG3	Device Configuration Register #3	Section 8.6.35
24h	DEV_CONFIG4	Device Configuration Register #4	Section 8.6.36
25h	DEV_CONFIG5	Device Configuration Register #5	Section 8.6.37
26h	DEV_CONFIG6	Device Configuration Register #6	Section 8.6.38
27h	FAULT_MASK	Fault Mask register	Section 8.6.39
28h	EN_WB_OFF	Enable Off-state Wire-break fault per channel	Section 8.6.40
29h	EN_WB_ON	Enable On-state Wire-break fault per channel	Section 8.6.41
2Ah	EN_SHRT_VS	Enable Output Short_to-VS fault per channel	Section 8.6.42
2Bh	ADC_ISNS_DIS	ADC conversion disable ISNS channels	Section 8.6.43
2Ch	ADC_TSNS_DIS	ADC conversion disable TSNS channels	Section 8.6.44
2Dh	ADC_VSNS_DIS	ADC conversion disable VSNS channels	Section 8.6.45
2Eh	ADC_CONFIG1	ADC configuration - disable conversion	Section 8.6.46
2Fh	CRC_CONFIG	Configure CRC	Section 8.6.47

Complex bit access types are encoded to fit into small table cells. Table 8-13 shows the codes that are used for access types in this section.

Table 8-13 TPS274C65 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RC	R C	Read to Clear
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

8.6.1 FAULT_TYPE_STAT Register (Offset = 0h) [Reset = 80h]

FAULT_TYPE_STAT is shown in Table 8-14.

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The register reports the fault type in any of the channels (OR of all channels)

Table 8-14 FAULT_TYPE_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SUPPLY_FLT	R	1h	The bit is set if either the VDD_UVLO or VS_UV are faults occur. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_GLOBAL_TYPE register is read and the fault condition no longer exists. 0h = no UV fault in VDD, VINT or VS 1h = UV fault in VDD, VINT or VS
6	RVRS_BLK_FLT	R	0h	The bit is set if there is a reverse current fault in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the RVRS_BLK_CH_STAT register is read and the fault condition no longer exists. 0h = no reverse current blocking fault in any of the channels 1h = reverse current blocking fault in one of the channels
5	CHAN_TSD	R	0h	The bit is set if there is a thermal shutdown fault due to thermal overload in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the THERMAL_SD_CH_STAT register is read and the fault condition no longer exists. 0h = no thermal shutdown fault in any of the channels 1h = thermal shutdown fault in one of the channels
4	ILIMIT_FLT	R	0h	The bit is set if there is a current limit fault due to ovecurrent in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the ILIMIT_CH_STAT register is read and the fault condition no longer exists. 0h = no current limit (overcurrent) fault in any of the channels 1h = current limit (overcurrent) fault in one of the channels
3	WB_ON_FLT	R	0h	The bit is set if there is a wire break in the on state fault in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the WB_ON_CH_STAT register is read and the fault condition no longer exists 0h = no on-state wire-break fault in any of the channels 1h = on-state wire-break fault in one of the channels
2	WB_OFF_FLT	R	0h	The bit is set if either there is a wire break in the off-state fault in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the WB_OFF_CH_STAT register is read and the fault condition no longer exists 0h = no off-state wire-break fault in any of the channels 1h = off-state wire-break fault in one of the channels
1	SHRT_VS_FLT	R	0h	The bit is set if there is a short to VS supply in the off-state fault in any one of the channels. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the SHRT_VS_CH_STAT register is read and the fault condition no longer exists 0h = no off-state short to VS fault in any of the channels 1h = off-state short to VS fault in one of the channels
0	GLOBAL_ERR_WRN	R	0h	The bit is set if there is a global fault reported in the FLT_GLOBAL_TYPE register (SPI error, watchdog error, VS_UV_WRN fault or chip thermal warning occurs. If FLT_LTCH_DIS bit is set, then the fault bit is latched and is cleared only when the FLT_GLOBAL_TYPE register is read and the fault condition no longer exists. 0h = no global fault (SPI error, watchdog error, VS_UV_WRN fault or chip thermal warning) 1h = One of the following errors have occurred: SPI error, watchdog error, VS_UV_WRN fault or chip thermal warning

8.6.2 FAULT_CH_STAT Register (Offset = 1h) [Reset = 00h]

FAULT_CH_STAT is shown in Table 8-15.

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The register reports faulted channel(s) (OR of all fault types in each channel)

Table 8-15 FAULT_CH_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	CH4	R	0h	The bit is set if any type of fault (RVRS_BLK, THERMAL_SD_CH, ILIMIT, WB_ON, WB_OFF, SHRT_VS) occurs in CH4 0h = No fault in CH4 1h = One or more fault has occurred in CH4
2	CH3	R	0h	The bit is set if any type of fault (RVRS_BLK, THERMAL_SD_CH, ILIMIT, WB_ON, WB_OFF, SHRT_VS) occurs in CH3 0h = No fault in CH4 1h = One or more fault has occurred in CH2
1	CH2	R	0h	The bit is set if any type of fault (RVRS_BLK, THERMAL_SD_CH, ILIMIT, WB_ON, WB_OFF, SHRT_VS) occurs in CH2 0h = No fault in CH4 1h = One or more fault has occurred in CH3
0	CH1	R	0h	The bit is set if any type of fault (RVRS_BLK, THERMAL_SD_CH, ILIMIT, WB_ON, WB_OFF, SHRT_VS) occurs in CH1 0h = No fault in CH4 1h = One or more fault has occurred in CH1

8.6.3 FAULT_GLOBAL_TYPE Register (Offset = 2h) [Reset = 47h]

FAULT_GLOBAL_TYPE is shown in Table 8-16.

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The register reports the type of global fault that has occurred in the IC

Table 8-16 FAULT_GLOBAL_TYPE Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	POR	RC	1h	The bit is indicative of whether a power on reset has occurred. 0h = There is no power-on reset anytime after the last register read The register bit is cleared on read, so if read again and the bit is 0, means that no power-on reset has occurred since the read. 1h = A power-on reset has occurred since the last register read.
5	CHIP_THERMALSD	RC	0h	The bit is set if the chip thermal warning is triggered at any time. The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and the chip thermal shutdown error condition is removed 0h = No chip thermal warning 1h = Chip thermal warning threshold exceeded
4	SPI_ERR	RC	0h	The bit is set if there is an SPI communication error either from format, clock or CRC errors.The fault bit is latched and cleared only after read and the error is removed. 0h = No SPI communication error fault 1h = SPI communication error either from format, clock or CRC has occurred
3	WD_ERR	RC	0h	The bit is set if the watchdog timeout on SPI read or write occurs. The fault bit is latched and cleared only after read and the error is removed. 0h = No SPI interface watchdog error 1h = SPI watchdog timeout error has occurred
2	VDD_UVLO	RC	1h	The bit is set if VDD supply is below the UVLO threshold at any time. The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and the UVLO condition is removed 0h = No VDD UVLO fault 1h = VDD UVLO fault
1	VS_UV_WRN	RC	1h	The bit is set if VS supply is below the UV warning (UV_WRN) threshold at any time. The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and the UV condition is removed 0h = No VS UV_WRN fault 1h = VS UV_WRN fault
0	VS_UV	RC	1h	The bit is set if VS supply is below the UV threshold at any time. The fault bit is cleared if the GLOBAL_FAULT_TYPE register is read and the UV condition is removed 0h = No VS UV fault 1h = VS UV fault

8.6.4 SHRT_VS_CH_STAT Register (Offset = 3h) [Reset = 00h]

SHRT_VS_CH_STAT is shown in Table 8-17.

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The register reports faulted channel(s) with the off-state short-to-supply fault

Table 8-17 SHRT_VS_CH_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	SHRT_VS_CH4	RC	0h	The bit is set if any short to supply (VS) fault has occurred at any time in CH4. The fault is latched and cleared when the SHRT_VS_CH_STAT register is read and fault condition does not exist anymore. 0h = No fault in CH4 1h = Short to VS fault has occurred in CH4
2	SHRT_VS_CH3	RC	0h	The bit is set if any short to supply (VS) fault has occurred at any time in CH3. The fault is latched and cleared when the SHRT_VS_CH_STAT register is read and fault condition does not exist anymore. 0h = No fault in CH4 1h = Short to VS fault has occurred in CH3
1	SHRT_VS_CH2	RC	0h	The bit is set if any short to supply (VS) fault has occurred at any time in CH2. The fault is latched and cleared when the SHRT_VS_CH_STAT register is read and fault condition does not exist anymore. 0h = No fault in CH4 1h = Short to VS fault has occurred in CH2
0	SHRT_VS_CH1	RC	0h	The bit is set if any short to supply (VS) fault has occurred at any time in CH1. The fault is latched and cleared when the SHRT_VS_CH_STAT register is read and fault condition does not exist anymore. 0h = No fault in CH4 1h = Short to VS fault has occurred in CH1

8.6.5 WB_OFF_CH_STAT Register (Offset = 4h) [Reset = 00h]

WB_OFF_CH_STAT is shown in Table 8-18.

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The register reports faulted channel(s) with the off-state wire-break fault

Table 8-18 WB_OFF_CH_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	WB_OFF_CH4	RC	0h	The bit is set if the wire break (open load) fault in off-state has occurred at any time in CH4. The fault is latched and cleared when the WB_OFF_CH_STAT register is read and fault condition does not exist anymore. 0h = No wire-break (off-state) fault in CH4 1h = Wire break (open load) fault in off-state has occurred in CH4
2	WB_OFF_CH3	RC	0h	The bit is set if the wire break (open load) fault in off-state has occurred at any time in CH3. The fault is latched and cleared when the WB_OFF_CH_STAT register is read and fault condition does not exist anymore. 0h = No wire-break (off-state) fault in CH3 1h = Wire break (open load) fault in off-state has occurred in CH3
1	WB_OFF_CH2	RC	0h	The bit is set if the wire break (open load) fault in off-state has occurred at any time in CH2. The fault is latched and cleared when the WB_OFF_CH_STAT register is read and fault condition does not exist anymore. 0h = No wire-break (off-state) fault in CH2 1h = Wire break (open load) fault in off-state has occurred in CH2
0	WB_OFF_CH1	RC	0h	The bit is set if the wire break (open load) fault in off-state has occurred at any time in CH1. The fault is latched and cleared when the WB_OFF_CH_STAT register is read and fault condition does not exist anymore. 0h = No wire-break (off-state) fault in CH1 1h = Wire break (open load) fault in off-state has occurred in CH1

8.6.6 WB_ON_CH_STAT Register (Offset = 5h) [Reset = 00h]

WB_ON_CH_STAT is shown in Table 8-19.

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The register reports faulted channel(s) with the on-state wire-break fault

Table 8-19 WB_ON_CH_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	WB_ON_CH4	RC	0h	The bit is set if the wire break (open load) fault in off-state has occurred at any time in CH4. The fault is latched and cleared when the WB_OFF_CH_STAT register is read and fault condition does not exist anymore. 0h = No wire-break (on-state) fault in CH4 1h = Wire break (open load) fault in on-state has occurred in CH4
2	WB_ON_CH3	RC	0h	The bit is set if the wire break (open load) fault in off-state has occurred at any time in CH3. The fault is latched and cleared when the WB_OFF_CH_STAT register is read and fault condition does not exist anymore. 0h = No wire-break (on-state) fault in CH3 1h = Wire break (open load) fault in on-state has occurred in CH3
1	WB_ON_CH2	RC	0h	The bit is set if the wire break (open load) fault in off-state has occurred at any time in CH2. The fault is latched and cleared when the WB_OFF_CH_STAT register is read and fault condition is cleared. 0h = No wire-break (on-state) fault in CH2 1h = Wire break (open load) fault in on-state has occurred in CH2
0	WB_ON_CH1	RC	0h	The bit is set if the wire break (open load) fault in off-state has occurred at any time in CH1. The fault is latched and cleared when the WB_OFF_CH_STAT register is read and fault condition does not exist anymore. 0h = No wire-break (on-state) fault in CH1 1h = Wire break (open load) fault in on-state has occurred in CH1

8.6.7 ILIMIT_CH_STAT Register (Offset = 6h) [Reset = 00h]

ILIMIT_CH_STAT is shown in Table 8-20.

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The register reports faulted channel(s) with the current limit fault

Table 8-20 ILIMIT_CH_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	ILIMIT_CH4	RC	0h	The bit is set if current limiting due to overcurrent has occurred at any time in CH4. The fault is latched and cleared when the ILIMIT_CH_STAT register is read and fault condition does not exist anymore. 0h = No current limit fault in CH4 1h = Current limit due to overcurrent fault has occurred in CH4
2	ILIMIT_CH3	RC	0h	The bit is set if current limiting due to overcurrent has occurred at any time in CH3. The fault is latched and cleared when the ILIMIT_CH_STAT register is read and fault condition does not exist anymore. 0h = No current limit fault in CH3 1h = Current limit due to overcurrent fault has occurred in CH3
1	ILIMIT_CH2	RC	0h	The bit is set if current limiting due to overcurrent has occurred at any time in CH2. The fault is latched and cleared when the ILIMIT_CH_STAT register is read and fault condition does not exist anymore. 0h = No current limit fault in CH2 1h = Current limit due to overcurrent fault has occurred in CH2
0	ILIMIT_CH1	RC	0h	The bit is set if current limiting due to overcurrent has occurred at any time in CH1. The fault is latched and cleared when the ILIMIT_CH_STAT register is read and fault condition does not exist anymore. 0h = No current limit fault in CH1 1h = Current limit due to overcurrent fault has occurred in CH1

8.6.8 THERMAL_SD_CH_STAT Register (Offset = 7h) [Reset = 00h]

THERMAL_SD_CH_STAT is shown in Table 8-21.

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The register reports faulted channel(s) with the thermal shutdown fault

Table 8-21 THERMAL_SD_CH_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	THERMAL_SD_CH4	RC	0h	The bit is set if the thermal shutdown has occurred at any time in CH4. The fault is latched and cleared when the THERMAL_SD_CH_STAT register is read and channel temperature has fallen below the thermal shutdown reset threshold. 0h = No thermal shutdown fault in CH4 1h = Thermal shudtwon has occurred in CH4
2	THERMAL_SD_CH3	RC	0h	The bit is set if the thermal shutdown has occurred at any time in CH3. The fault is latched and cleared when the THERMAL_SD_CH_STAT register is read and channel temperature has fallen below the thermal shutdown reset threshold. 0h = No thermal shutdown fault in CH3 1h = Thermal shudtwon has occurred in CH3
1	THERMAL_SD_CH2	RC	0h	The bit is set if the thermal shutdown has occurred at any time in CH2. The fault is latched and cleared when the THERMAL_SD_CH_STAT register is read and channel temperature has fallen below the thermal shutdown reset threshold. 0h = No thermal shutdown fault in CH2 1h = Thermal shudtwon has occurred in CH2
0	THERMAL_SD_CH1	RC	0h	The bit is set if the thermal shutdown has occurred at any time in CH1. The fault is latched and cleared when the THERMAL_SD_CH_STAT register is read and channel temperature has fallen below the thermal shutdown reset threshold. 0h = No thermal shutdown fault in CH1 1h = Thermal shudtwon has occurred in CH1

8.6.9 THERMAL_WRN_CH_STAT Register (Offset = 8h) [Reset = 00h]

THERMAL_WRN_CH_STAT is shown in Table 8-22.

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The register reports channel(s) with the temperature above thermal warning threshold

Table 8-22 THERMAL_WRN_CH_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	THERMAL_WRN_CH4	R	0h	The bit is set if FET temperature is above the overtemperature warning threshold in CH4. The bit is cleared when over-temperature earning condition does not exist anymore. 0h = FET temperatire below over-temperature warning threshold in CH4 1h = FET temperatire above over-temperature warning threshold in CH4
2	THERMAL_WRN_CH3	R	0h	The bit is set if FET temperature is above the overtemperature warning threshold in CH3. The bit is cleared when over-temperature earning condition does not exist anymore. 0h = FET temperatire below over-temperature warning threshold in CH4 1h = FET temperatire above over-temperature warning threshold in CH3
1	THERMAL_WRN_CH2	R	0h	The bit is set if FET temperature is above the overtemperature warning threshold in CH2. The bit is cleared when over-temperature earning condition does not exist anymore. 0h = FET temperatire below over-temperature warning threshold in CH2 1h = FET temperatire above over-temperature warning threshold in CH2
0	THERMAL_WRN_CH1	R	0h	The bit is set if FET temperature is above the overtemperature warning threshold in CH1. The bit is cleared when over-temperature earning condition does not exist anymore. 0h = FET temperatire below over-temperature warning threshold in CH1 1h = FET temperatire above over-temperature warning threshold in CH1

8.6.10 RVRS_BLK_CH_STAT Register (Offset = 9h) [Reset = 00h]

RVRS_BLK_CH_STAT is shown in Table 8-23.

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The register reports faulted channel(s) with the reverse current flow (blocked) fault

Table 8-23 RVRS_BLK_CH_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	RVRS_BLK_CH4	RC	0h	The bit is set if the reverse current fault (blocked) has occurred at any time in CH4. The fault is latched and cleared when the RVRS_BLK_CH_STAT register is read. 0h = No reverse current fault in CH4 1h = Reverse current flow (blocked) fault in on-state has occurred in CH4
2	RVRS_BLK_CH3	RC	0h	The bit is set if the reverse current fault (blocked) has occurred at any time in CH3. The fault is latched and cleared when the RVRS_BLK_CH_STAT register is read. 0h = No reverse current fault in CH3 1h = Reverse current flow (blocked) fault in on-state has occurred in CH4
1	RVRS_BLK_CH2	RC	0h	The bit is set if the reverse current fault (blocked) has occurred at any time in CH2. The fault is latched and cleared when the RVRS_BLK_CH_STAT register is read. 0h = No reverse current fault in CH2 1h = Reverse current flow (blocked) fault in on-state has occurred in CH4
0	RVRS_BLK_CH1	RC	0h	The bit is set if the reverse current fault (blocked) has occurred at any time in CH1. The fault is latched and cleared when the RVRS_BLK_CH_STAT register is read. 0h = No reverse current fault in CH1 1h = Reverse current flow (blocked) fault in on-state has occurred in CH4

8.6.11 ADC_RESULT_CH1_I Register (Offset = Bh) [Reset = 00h]

ADC_RESULT_CH1_I is shown in Table 8-24.

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The register records ADC conversion result for current sense of CH1

Table 8-24 ADC_RESULT_CH1_I Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_ISNS_CH1	R	0h	ADC result (8-bits) from the conversion of the current in CH1

8.6.12 ADC_RESULT_CH1_I_LSB Register (Offset = Ch) [Reset = 00h]

ADC_RESULT_CH1_I_LSB is shown in Table 8-25.

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The register records ADC conversion result for current sense of CH1 (Two LSBs)

Table 8-25 ADC_RESULT_CH1_I_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	Reserved
1-0	ADC_ISNS_CH1_LSB	R	0h	Least Significant Bits for ADC result from conversion of the current in CH1

8.6.13 ADC_RESULT_CH2_I Register (Offset = Dh) [Reset = 00h]

ADC_RESULT_CH2_I is shown in Table 8-26.

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The register records ADC conversion result for current sense of CH2

Table 8-26 ADC_RESULT_CH2_I Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_ISNS_CH2	R	0h	ADC result (8-bits) from the conversion of the current in CH2

8.6.14 ADC_RESULT_CH2_I_LSB Register (Offset = Eh) [Reset = 00h]

ADC_RESULT_CH2_I_LSB is shown in Table 8-27.

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The register records ADC conversion result for current sense of CH2 (Two LSBs)

Table 8-27 ADC_RESULT_CH2_I_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	Reserved
1-0	ADC_ISNS_CH2_LSB	R	0h	Least Significant Bits for ADC result from conversion of the current in CH2

8.6.15 ADC_RESULT_CH3_I Register (Offset = Fh) [Reset = 00h]

ADC_RESULT_CH3_I is shown in Table 8-28.

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The register records ADC conversion result for current sense of CH3

Table 8-28 ADC_RESULT_CH3_I Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_ISNS_CH3	R	0h	ADC result (8-bits) from the conversion of the current in CH3

8.6.16 ADC_RESULT_CH3_I_LSB Register (Offset = 10h) [Reset = 00h]

ADC_RESULT_CH3_I_LSB is shown in Table 8-29.

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The register records ADC conversion result for current sense of CH3 (Two LSBs)

Table 8-29 ADC_RESULT_CH3_I_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	Reserved
1-0	ADC_ISNS_CH3_LSB	R	0h	Least Significant Bits for ADC result from conversion of the current in CH3

8.6.17 ADC_RESULT_CH4_I Register (Offset = 11h) [Reset = 00h]

ADC_RESULT_CH4_I is shown in Table 8-30.

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The register records ADC conversion result for current sense of CH4

Table 8-30 ADC_RESULT_CH4_I Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_ISNS_CH4	R	0h	ADC result (8-bits) from the conversion of the current in CH4

8.6.18 ADC_RESULT_CH4_I_LSB Register (Offset = 12h) [Reset = 00h]

ADC_RESULT_CH4_I_LSB is shown in Table 8-31.

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The register records ADC conversion result for current sense of CH4 (Two LSBs)

Table 8-31 ADC_RESULT_CH4_I_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	Reserved
1-0	ADC_ISNS_CH4_LSB	R	0h	Least Significant Bits for ADC result from conversion of the current in CH4

8.6.19 ADC_RESULT_CH1_T Register (Offset = 13h) [Reset = 00h]

ADC_RESULT_CH1_T is shown in Table 8-32.

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The register records ADC conversion result for temperature sense of CH1

Table 8-32 ADC_RESULT_CH1_T Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_TSNS_CH1	R	0h	ADC result (8-bits) from the conversion of the temperature in CH1

8.6.20 ADC_RESULT_CH2_T Register (Offset = 14h) [Reset = 00h]

ADC_RESULT_CH2_T is shown in Table 8-33.

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The register records ADC conversion result for temperature sense of CH2

Table 8-33 ADC_RESULT_CH2_T Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_TSNS_CH2	R	0h	ADC result (8-bits) from the conversion of the temperature in CH2

8.6.21 ADC_RESULT_CH3_T Register (Offset = 15h) [Reset = 00h]

ADC_RESULT_CH3_T is shown in Table 8-34.

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The register records ADC conversion result for temperature sense of CH3

Table 8-34 ADC_RESULT_CH3_T Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_TSNS_CH3	R	0h	ADC result (8-bits) from the conversion of the temperature in CH3

8.6.22 ADC_RESULT_CH4_T Register (Offset = 16h) [Reset = 00h]

ADC_RESULT_CH4_T is shown in Table 8-35.

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The register records ADC conversion result for temperature sense of CH4

Table 8-35 ADC_RESULT_CH4_T Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_TSNS_CH4	R	0h	ADC result (8-bits) from the conversion of the temperature in CH4

8.6.23 ADC_RESULT_CH1_V Register (Offset = 17h) [Reset = 00h]

ADC_RESULT_CH1_V is shown in Table 8-36.

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The register records ADC conversion result for voltage sense of CH1

Table 8-36 ADC_RESULT_CH1_V Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_VSNS_CH1	R	0h	ADC result (8-bits) from the conversion of the voltage in CH1

8.6.24 ADC_RESULT_CH2_V Register (Offset = 18h) [Reset = 00h]

ADC_RESULT_CH2_V is shown in Table 8-37.

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The register records ADC conversion result for voltage sense of CH2

Table 8-37 ADC_RESULT_CH2_V Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_VSNS_CH2	R	0h	ADC result (8-bits) from the conversion of the voltage in CH2

8.6.25 ADC_RESULT_CH3_V Register (Offset = 19h) [Reset = 00h]

ADC_RESULT_CH3_V is shown in Table 8-38.

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The register records ADC conversion result for voltage sense of CH3

Table 8-38 ADC_RESULT_CH3_V Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_VSNS_CH3	R	0h	ADC result (8-bits) from the conversion of the voltage in CH3

8.6.26 ADC_RESULT_CH4_V Register (Offset = 1Ah) [Reset = 00h]

ADC_RESULT_CH4_V is shown in Table 8-39.

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The register records ADC conversion result for voltage sense of CH4

Table 8-39 ADC_RESULT_CH4_V Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_VSNS_CH4	R	0h	ADC result (8-bits) from the conversion of the voltage in CH4

8.6.27 ADC_RESULT_VS Register (Offset = 1Bh) [Reset = 00h]

ADC_RESULT_VS is shown in Table 8-40.

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The register records ADC conversion result for supply voltage sense

Table 8-40 ADC_RESULT_VS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	ADC_VS_SNS	R	0h	ADC result (8-bits) from the conversion of the supply voltage input (VS pin)

8.6.28 ADC_RESULT_VS_LSB Register (Offset = 1Ch) [Reset = 00h]

ADC_RESULT_VS_LSB is shown in Table 8-41.

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The register records ADC conversion result for supply voltage sense (Two LSBs)

Table 8-41 ADC_RESULT_VS_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	Reserved
1-0	ADC_VS_SNS_CH4_LSB	R	0h	Least Significant Bits for ADC result from conversion of the supply voltage input (VS pin)

8.6.29 SW_STATE Register (Offset = 1Dh) [Reset = 00h]

SW_STATE is shown in Table 8-42.

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The register sets the switch state (ON/OFF) of each output channel. The switch state bits in the SPI frame are ignored when a write to this register is performed (only the contents of the DATA_IN field of the SPI frame are used to update the switch state)

Table 8-42 SW_STATE Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	CH4_ON	R/W	0h	Set this bit to 1 to turn on the FET and CH4 output ON 0h = CH4 Output set to OFF (FET is OFF). The switch state bits in the SPI frame are ignored 1h = CH4 Output set to ON (FET is ON). The switch state bits in the SPI frame are ignored
2	CH3_ON	R/W	0h	Set this bit to 1 to turn on the FET and CH3 output ON 0h = CH3 Output set to OFF (FET is OFF). The switch state bits in the SPI frame are ignored. 1h = CH3 Output set to ON (FET is ON). The switch state bits in the SPI frame are ignored
1	CH2_ON	R/W	0h	Set this bit to 1 to turn on the FET and CH2 output ON 0h = CH2 Output set to OFF (FET is OFF). The switch state bits in the SPI frame are ignored 1h = CH2 Output set to ON (FET is ON). The switch state bits in the SPI frame are ignored
0	CH1_ON	R/W	0h	Set this bit to 1 to turn on the FET and CH1 output ON 0h = CH1 Output set to OFF (FET is OFF). The switch state bits in the SPI frame are ignored 1h = CH1 Output set to ON (FET is ON). The switch state bits in the SPI frame are ignored

8.6.30 LED1_4_CTL Register (Offset = 1Eh) [Reset = 00h]

LED1_4_CTL is shown in Table 8-43.

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The register sets the LEDs ON or OFF

Table 8-43 LED1_4_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	LED4_CTL	R/W	0h	Set this bit to 1 to turn on the LED4 Output Status indicator 0h = LED set to OFF 1h = LED set to ON
2	LED3_CTL	R/W	0h	Set this bit to 1 to turn on the LED3 Output Status indicator 0h = LED set to OFF 1h = LED set to ON
1	LED2_CTL	R/W	0h	Set this bit to 1 to turn on the LED2 Output Status indicator 0h = LED set to OFF 1h = LED set to ON
0	LED1_CTL	R/W	0h	Set this bit to 1 to turn on the LED1 Output Status indicator 0h = LED set to OFF 1h = LED set to ON

8.6.31 LED_5_8_CTL Register (Offset = 1Fh) [Reset = 00h]

LED_5_8_CTL is shown in Table 8-44.

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The register sets the LEDs ON or OFF

Table 8-44 LED_5_8_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	LED8_CTL	R/W	0h	Set this bit to 1 to turn on the LED8 Output Status indicator 0h = LED set to OFF 1h = LED set to ON
2	LED7_CTL	R/W	0h	Set this bit to 1 to turn on the LED7 Output Status indicator 0h = LED set to OFF 1h = LED set to ON
1	LED6_CTL	R/W	0h	Set this bit to 1 to turn on the LED6 Output Status indicator 0h = LED set to OFF 1h = LED set to ON
0	LED5_CTL	R/W	0h	Set this bit to 1 to turn on the LED5 Output Status indicator 0h = LED set to OFF 1h = LED set to ON

8.6.32 FS_SW_STATE Register (Offset = 20h) [Reset = 00h]

FS_SW_STATE is shown in Table 8-45.

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The register sets the switch state (ON/OFF) of each output channel in case of SPI_ERR or WD_ERR

Table 8-45 FS_SW_STATE Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	CH4_FS_ON	R/W	0h	Set this bit to 1 to turn on the CH4 FET and CH4 Output ON when WD_ERR fault has occurred 0h = CH4 Output set to OFF (FET is OFF) when WD_ERR occurs 1h = CH4 Output set to ON (FET is ON) when WD_ERR occurs
2	CH3_FS_ON	R/W	0h	Set this bit to 1 to turn on the CH3 FET and CH4 Output ON when WD_ERR fault has occurred 0h = CH3 Output set to OFF (FET is OFF) when WD_ERR occurs 1h = CH3 Output set to ON (FET is ON) when WD_ERR occurs
1	CH2_FS_ON	R/W	0h	Set this bit to 1 to turn on the CH2 FET and CH4 Output ON when WD_ERR fault has occurred 0h = CH2 Output set to OFF (FET is OFF) whenWD_ERR occurs 1h = CH2 Output set to ON (FET is ON) when WD_ERR occurs
0	CH1_FS_ON	R/W	0h	Set this bit to 1 to turn on the CH1 FET and CH4 Output ON when WD_ERR fault has occurred 0h = CH1 Output set to OFF (FET is OFF) when WD_ERR occurs 1h = CH1 Output set to ON (FET is ON) when WD_ERR occurs

8.6.33 DEV_CONFIG1 Register (Offset = 21h) [Reset = 0Ah]

DEV_CONFIG1 is shown in Table 8-46.

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Current limit setting and duration of initial inrush level and time channel 1/2

Table 8-46 DEV_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	ILIM_DURATION_12	R/W	0h	Sets the delay period during with inrush current limit level applies (Ch1 and Ch2). 0h = 0ms 1h = 2ms 2h = 4ms 3h = 6ms 4h = 8ms 5h = 10ms 6h = 12ms 7h = 16ms 8h = 20ms 9h = 24ms Ah = 28ms Bh = 32ms Ch = 40ms Dh = 48ms Eh = 56ms Fh = 64ms
3-0	ILIM_REG_12	R/W	Ah	Sets the current limit regulation value during overcurrent or short circuit events (Ch1 and Ch2). 0h = 0.25A 1h = 0.33A 2h = 0.4A 3h = 0.48A 4h = 0.56A 5h = 0.67A 6h = 0.72A 7h = 0.85A 8h = 1A 9h = 1.1A Ah = 1.25A Bh = 1.5A Ch = 1.6A Dh = 1.75A Eh = 1.9A Fh = 2.2A

8.6.34 DEV_CONFIG2 Register (Offset = 22h) [Reset = 0Ah]

DEV_CONFIG2 is shown in Table 8-47.

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Current limit setting and duration of initial inrush level and time channel 3/4

Table 8-47 DEV_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	ILIM_DURATION_34	R/W	0h	Sets the delay period during with inrush current limit level applies (Ch3 and Ch4). 0h = 0ms 1h = 2ms 2h = 4ms 3h = 6ms 4h = 8ms 5h = 10ms 6h = 12ms 7h = 16ms 8h = 20ms 9h = 24ms Ah = 28ms Bh = 32ms Ch = 40ms Dh = 48ms Eh = 56ms Fh = 64ms
3-0	ILIM_REG_34	R/W	Ah	Sets the current limit regulation value during overcurrent or short circuit events(Ch3 and Ch4). 0h = 0.25A 1h = 0.33A 2h = 0.4A 3h = 0.48A 4h = 0.56A 5h = 0.67A 6h = 0.72A 7h = 0.85A 8h = 1A 9h = 1.1A Ah = 1.25A Bh = 1.5A Ch = 1.6A Dh = 1.75A Eh = 1.9A Fh = 2.2A

8.6.35 DEV_CONFIG3 Register (Offset = 23h) [Reset = 00h]

DEV_CONFIG3 is shown in Table 8-48.

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Device Configuration register - RCB function disable in all channels,Sense current range Inrush current Limit level config, Parallel chanel config Inrush current Limit level config, ILIM type config inrush or current limit duration

Table 8-48 DEV_CONFIG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RCB_DIS	R/W	0h	Setting this bit to 1, disable RCB function in all channels 0h = RCB FET gate output set per channel. 1h = Disables RCB function
6	ILIM_SET	R/W	0h	Set this bit to allow CH1/CH2 to have different current limit setting than CH3/CH4 0h = Current Limit / inrush deay the same for all channels as in register DEV_CONFIG1 1h = Current limit / inrsh delay set differenty for CH1/CH2 (as in DEV_CONFIG1) and C3/CH4 (DEV_CONFIG2)
5	ISNS_RANGE	R/W	0h	Sets the load current sense range - optimizing the current sense output 0h = Load current to be sensed less than or equal to 800 mA 1h = Load current to be sensed more than 800 mA
4	PARALLEL_34	R/W	0h	Set this bit to 1 to signal that channels 3 and 4 (CH3 and CH4) are paralleled. Write to this bit is valid only when all four SW_STATE bits are 0 and not rewritten to 1 in the same frame. 0h = CH3 and CH4 are not paralleled together 1h = CH3 and CH4 are paralleled together
3	PARALLEL_12	R/W	0h	Set this bit to 1 to signal that channels 1 and 2(CH1 and CH2) are paralleled. Write to this bit is valid only when all four SW_STATE bits are 0 and not rewritten to 1 in the same frame. 0h = CH1 and CH2 are not paralleled together 1h = CH1 and CH2 are paralleled together
2	ILIM_CONFIG	R/W	0h	Set this bit to 1 to have the ILIM duration applied as the period of inrush current limit or to set as the duration of current limiting before switching off the FET. 0h = ILIM duratiion set as the period of inrush current limit 1h = ILIM duration set as the period of current limiting before switching off FET
1-0	INRUSH_LIMIT	R/W	0h	Sets the inrush current limit level that applies during the duration of ILIM inrush duration. See table of inrush current limit level settings in the datasheet

8.6.36 DEV_CONFIG4 Register (Offset = 24h) [Reset = 02h]

DEV_CONFIG4 is shown in Table 8-49.

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Device Configuration register - Configuring WB_on_threshold current. WB_off PU current, Watchdog enable and timer duration

Table 8-49 DEV_CONFIG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	WD_EN	R/W	0h	The bit is set to enable the watchdog function 0h = Watchdog is disabled 1h = Watchdog function is enabled
6-5	WD_TO	R/W	0h	Sets the timeout period for the SPI watchdog monitor 0h = Watchdog timeout 400 us 1h = Watchdog timeout is 400 ms 2h = Watchdog timeout is 800 ms 3h = Watchdog timeout is 1200 ms
4-3	WB_OFF_PU	R/W	0h	Sets the pullup current value (at the OUTx pins) by the off-state wire-break (open load) detection circuit. 0h = I_pu is 50 uA 1h = I_pu is 100 uA 2h = I_pu is 200 uA 3h = I_pu is 500 uA
2-0	WB_ON_THD	R/W	2h	Sets the current threshold for on-state wire-break (open load) detection. See table of settings in the datasheet

8.6.37 DEV_CONFIG5 Register (Offset = 25h) [Reset = 00h]

DEV_CONFIG5 is shown in Table 8-50.

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Device Configuration register - Device Configuration register - Fault bit LATCH_mode enable, ,Wire break or short to VS blanking time in off-state,Sw_STATE config, fault latch with retry only on enable toggle.

Table 8-50 DEV_CONFIG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R	0h	Reserved
5	ADC_EN	R/W	0h	Setting this bit to 1, enables the ADC function 0h = ADC function disabled 1h = ADC enabled
4	AUTO_RETRY_DIS	R/W	0h	Setting this bit to 1, disables the auto-retry and latches the channel Output OFF on thermal shutdown of the channel occurs. Retry can be attempted by toggling enable. 0h = Auto-retry on thermal shutdown of the channel 1h = Latches the channel output off on thermal shutdown - retry on toggling enable.
3-2	WB_SVS_BLANK	R/W	0h	Sets the blanking time for wire-break (ON-state and OFF-state) and the short_to_VS faults before the fault is registered. 0h = Blanking time is 0.4 ms 1h = Blanking time is 1.0 ms 2h = Blanking time is 2.0 ms 3h = Blanking time is 4.0 ms
1	SW_FS_CFG	R/W	0h	Set this bit to 1 to have the outputs hold state when WD_ERR faults have occurred. Otherwise the device uses the FS_SW_STATE register bits. 0h = Switch (output) holds state 1h = Switch (output) state set by Sw_FS_STATE register when WD_ERR occurs
0	FLT_LTCH_DIS	R/W	0h	Set this bit to 1 to not latch the fault bits in the register and cleared on read. 0h = Fault bits latched and cleared only on read 1h = Fault bits not latched, cleared when the fault disappears

8.6.38 DEV_CONFIG6 Register (Offset = 26h) [Reset = 0Fh]

DEV_CONFIG6 is shown in Table 8-51.

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Device Configuration register - Per Channel RCB FET gate off configuration

Table 8-51 DEV_CONFIG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	RCB_CH4	R/W	1h	Bit determines the reverse current blocking FET gate control in CH4 0h = Reverse current blocking FET gate pulldown (CH4) is enabled (if RCB_DIS bit is not set) 1h = Reverse current blocking function in CH4 enabled (if RCB_DIS bit is not set)
2	RCB_CH3	R/W	1h	Bit determines the reverse current blocking FET gate control in CH3 0h = Reverse current blocking FET gate pulldown (CH3) is enabled (if RCB_DIS bit is not set) 1h = Reverse current blocking function in CH3 enabled (if RCB_DIS bit is not set)
1	RCB_CH2	R/W	1h	Bit determines the reverse current blocking FET gate control in CH2 0h = Reverse current blocking FET gate pulldown (CH2) is enabled (if RCB_DIS bit is not set) 1h = Reverse current blocking function in CH2 enabled (if RCB_DIS bit is not set)
0	RCB_CH1	R/W	1h	Bit determines the reverse current blocking FET gate control in CH1 0h = Reverse current blocking FET gate pulldown (CH1) is enabled (if RCB_DIS bit is not set) 1h = Reverse current blocking function in CH1 enabled (if RCB_DIS bit is not set)

8.6.39 FAULT_MASK Register (Offset = 27h) [Reset = 00h]

FAULT_MASK is shown in Table 8-52.

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The register allows masking of certain types of faults.

Table 8-52 FAULT_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MASK_SPI_ERR	R/W	0h	The bit is set to mask the SPI error (SPI_ERR) signaling in the FLT pin output and FAULT_TYPE_STAT register 0h = SPI error is signaled in FAULT_TYPE_STAT register and FLT pin 1h = FLT pin not impacted by SPI error, but SPI error will be signaled through FAULT_TYPE_STAT register
6	MASK_WD_ERR	R/W	0h	The bit is set to mask the SPI watchdog error (WD_ERR) signaling in the FLT pin output and FAULT_TYPE_STAT register 0h = SPI watchdog error is signaled in FAULT_TYPE_STAT register and FLT pin 1h = FLT pin not impacted by SPI error, but watchdog error will be signaled through FAULT_TYPE_STAT register
5	MASK_ILIMIT	R/W	0h	The bit is set to mask the signaling ILIMIT fault on the FLT pin 0h = Fault is signaled on the FLT pin on current limit occuring 1h = Current limit fault is not signaled (masked from) on the FLT pin
4	MASK_RVRS_BLK	R/W	0h	The bit is set to mask the signaling reverse current fault on the FLT pin 0h = Fault is signaled on the FLT pin on reverse current fault occuring 1h = Reverse current fault is not signaled (masked from) on the FLT pin
3	MASK_SHRT_VS	R/W	0h	The bit is set to mask the signaling off-state Short to VS fault on the FLT pin 0h = Short to VS Fault is signaled on the FLT pin on detecting the fault with the diagnostic 1h = Short to VS fault is not signaled (masked from) on the FLT pin
2	MASK_WB_OFF	R/W	0h	The bit is set to mask the signaling off-state wire-break fault on the FLT pin 0h = Off-state wire-break fault is signaled on the FLT pin on detecting the fault with the diagnostic 1h = Off-state wire-break fault is not signaled (masked from) on the FLT pin
1	MASK_WB_ON	R/W	0h	The bit is set to mask the signaling on-state wire-break fault on the FLT pin 0h = On-state wire-break fault is signaled on the FLT pin on detecting the fault with the diagnostic 1h = On-state wire-break fault is not signaled (masked from) on the FLT pin
0	MASK_VS_UV	R/W	0h	The bit is set to mask the supply voltage VS UV fault signaling on the FLT pin output. 0h = VS UV fault is signaled on the FLT pin on detecting the fault with the diagnostic 1h = VS UV fault is not signaled (masked from) on the FLT pin

8.6.40 EN_WB_OFF Register (Offset = 28h) [Reset = 00h]

EN_WB_OFF is shown in Table 8-53.

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Enables diagnostic of the wire-break (off-state) faults in the fault registers

Table 8-53 EN_WB_OFF Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	WB_OFF_CH4_EN	R/W	0h	Set this bit to 1 to enable the wire-break (off-state) fault in CH4 0h = Wire-break (off-state) fault diagnostic in CH4 not enabled 1h = Wire-break (off-state) fault diagnostic in CH4 is enabled
2	WB_OFF_CH3_EN	R/W	0h	Set this bit to 1 to enable the wire-break (off-state) fault in CH3 0h = Wire-break (off-state) fault diagnostic in CH3 not enabled 1h = Wire-break (off-state) fault diagnostic in CH3 is enabled
1	WB_OFF_CH2_EN	R/W	0h	Set this bit to 1 to enable the wire-break (off-state) fault in CH2 0h = Wire-break (off-state) fault diagnostic in CH2 not enabled 1h = Wire-break (off-state) fault diagnostic in CH2 is enabled
0	WB_OFF_CH1_EN	R/W	0h	Set this bit to 1 to enable the wire-break (off-state) fault in CH1 0h = Wire-break (off-state) fault diagnostic in CH1 not enabled 1h = Wire-break (off-state) fault diagnostic in CH1 is enabled

8.6.41 EN_WB_ON Register (Offset = 29h) [Reset = 00h]

EN_WB_ON is shown in Table 8-54.

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The register allows masking of On-state Wire-break fault per channel

Table 8-54 EN_WB_ON Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	WB_ON_CH4_EN	R/W	0h	Set this bit to 1 to enable the wire-break (off-state) fault diagnostic in CH4 0h = Wire-break (off-state) fault diagnostic in CH4 not enabled 1h = Wire-break (off-state) fault diagnostic in CH4 is enabled
2	WB_ON_CH3_EN	R/W	0h	Set this bit to 1 to enable the wire-break (off-state) fault diagnostic in CH3 0h = Wire-break (off-state) fault diagnostic in CH3 not enabled 1h = Wire-break (off-state) fault diagnostic in CH3 is enabled
1	WB_ON_CH2_EN	R/W	0h	Set this bit to 1 to enable the wire-break (off-state) fault diagnostic in CH2 0h = Wire-break (off-state) fault diagnostic in CH2 not enabled 1h = Wire-break (off-state) fault diagnostic in CH2 is enabled
0	WB_ON_CH1_EN	R/W	0h	Set this bit to 1 to enable the wire-break (off-state) fault diagnostic in CH1 0h = Wire-break (off-state) fault diagnostic in CH1 not enabled 1h = Wire-break (off-state) fault diagnostic in CH1 is enabled

8.6.42 EN_SHRT_VS Register (Offset = 2Ah) [Reset = 00h]

EN_SHRT_VS is shown in Table 8-55.

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The register allows masking of output short to supply (VS) fault per channel

Table 8-55 EN_SHRT_VS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	SHRT_VS_CH4_EN	R/W	0h	Set this bit to 1 to enable the short_to_VS (off-state) fault diagnostic in CH4 0h = short_to_VS (off-state) fault diagnostic in CH4 not enabled 1h = short_to_VS (off-state) fault diagnostic in CH4 enabled
2	SHRT_VS_CH3_EN	R/W	0h	Set this bit to 1 to enable the short_to_VS (off-state) fault diagnostic in CH3 0h = short_to_VS (off-state) fault diagnostic in CH3 not enabled 1h = short_to_VS (off-state) fault diagnostic in CH3 enabled
1	SHRT_VS_CH2_EN	R/W	0h	Set this bit to 1 to enable the short_to_VS (off-state) fault diagnostic in CH2 0h = short_to_VS (off-state) fault diagnostic in CH2 not enabled 1h = short_to_VS (off-state) fault diagnostic in CH2 enabled
0	SHRT_VS_CH1_EN	R/W	0h	Set this bit to 1 to enable the short_to_VS (off-state) fault diagnostic in CH1 0h = short_to_VS (off-state) fault diagnostic in CH1 not enabled 1h = short_to_VS (off-state) fault diagnostic in CH1 enabled

8.6.43 ADC_ISNS_DIS Register (Offset = 2Bh) [Reset = 00h]

ADC_ISNS_DIS is shown in Table 8-56.

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Allows disabling the ADC conversion of ISNS on a per channel basis

Table 8-56 ADC_ISNS_DIS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	ISNS_DIS_CH4	R/W	0h	Set this bit to 1 disable ISNS_CH4 conversion 0h = ISNS_CH4 ADC conversion included 1h = ISNS_CH4 ADC conversion disabled
2	ISNS_DIS_CH3	R/W	0h	Set this bit to 1 disable ISNS_CH3 conversion 0h = ISNS_CH3 ADC conversion included 1h = ISNS_CH3 ADC conversion disabled
1	ISNS_DIS_CH2	R/W	0h	Set this bit to 1 disable ISNS_CH2 conversion 0h = ISNS_CH2 ADC conversion included 1h = ISNS_CH2 ADC conversion disabled
0	ISNS_DIS_CH1	R/W	0h	Set this bit to 1 disable ISNS_CH1 conversion 0h = ISNS_CH1 ADC conversion included 1h = ISNS_CH1 ADC conversion disabled

8.6.44 ADC_TSNS_DIS Register (Offset = 2Ch) [Reset = 00h]

ADC_TSNS_DIS is shown in Table 8-57.

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Allows disabling the ADC conversion of TSNS on a per channel basis

Table 8-57 ADC_TSNS_DIS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	TSNS_DIS_CH4	R/W	0h	Set this bit to 1 disable TSNS_CH4 conversion 0h = TSNS_CH4 ADC conversion included 1h = TSNS_CH4 ADC conversion disabled
2	TSNS_DIS_CH3	R/W	0h	Set this bit to 1 disable TSNS_CH3 conversion 0h = TSNS_CH3 ADC conversion included 1h = TSNS_CH3 ADC conversion disabled
1	TSNS_DIS_CH2	R/W	0h	Set this bit to 1 disable TSNS_CH2 conversion 0h = TSNS_CH2 ADC conversion included 1h = TSNS_CH2 ADC conversion disabled
0	TSNS_DIS_CH1	R/W	0h	Set this bit to 1 disable TSNS_CH1 conversion 0h = TSNS_CH1 ADC conversion included 1h = TSNS_CH1 ADC conversion disabled

8.6.45 ADC_VSNS_DIS Register (Offset = 2Dh) [Reset = 00h]

ADC_VSNS_DIS is shown in Table 8-58.

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Allows disabling the ADC conversion of VSNS on a per channel basis

Table 8-58 ADC_VSNS_DIS Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	VSNS_DIS_CH4	R/W	0h	Set this bit to 1 disable VSNS_CH4 conversion 0h = VSNS_CH4 ADC conversion included 1h = VSNS_CH4 ADC conversion disabled
2	VSNS_DIS_CH3	R/W	0h	Set this bit to 1 disable VSNS_CH3 conversion 0h = VSNS_CH3 ADC conversion included 1h = VSNS_CH3 ADC conversion disabled
1	VSNS_DIS_CH2	R/W	0h	Set this bit to 1 disable VSNS_CH2 conversion 0h = VSNS_CH2 ADC conversion included 1h = VSNS_CH2 ADC conversion disabled
0	VSNS_DIS_CH1	R/W	0h	Set this bit to 1 disable VSNS_CH1 conversion 0h = VSNS_CH1 ADC conversion included 1h = VSNS_CH1 ADC conversion disabled

8.6.46 ADC_CONFIG1 Register (Offset = 2Eh) [Reset = 00h]

ADC_CONFIG1 is shown in Table 8-59.

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ADC configuration - disable conversion of measurements not needed.

Table 8-59 ADC_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3	ADC_TSNS_DIS	R/W	0h	Set this bit to 1 to disable the ADC TSNS functionality 0h = TSNS ADC functionality enabled 1h = TSNS ADC functionality is disabled
2	ADC_VSNS_DIS	R/W	0h	Set this bit to 1 to disable the VSNS ADC functionality 0h = VSNS ADC functionality enabled 1h = VSNS ADC functionality is disabled
1	ADC_ISNS_DIS	R/W	0h	Set this bit to 1 to disable ISNS ADC functionality 0h = ISNS ADC functionality enabled 1h = ISNS ADC functionality is disabled
0	ADC_VS_DIS	R/W	0h	Set this bit to 1 to disable supply voltage V_VS conversion in the ADC conversion sequence. 0h = Include supply voltage V_VS conversion in the sequence 1h = No conversion of suppy voltage V_VS

8.6.47 CRC_CONFIG Register (Offset = 2Fh) [Reset = 00h]

CRC_CONFIG is shown in Table 8-60.

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Configure CRC

Table 8-60 CRC_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	Reserved
1	D24BIT	R/W	0h	Set this bit to 1 to use 24-bit SPI command frame in daisy chain mode 0h = 16-bit frame and No CRC check of SPI command frame 1h = 24-bit frame with the possibility of CRC check
0	CRC_EN	R/W	0h	Set this bit to 1 to enable CRC check of SPI command frame. 0h = No CRC check of SPI command frame 1h = CRC check of SPI command frame enabled