JAJSKH0C April   2023  – February 2024 TPS274C65

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1.     7
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 SPI Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Diagrams
      2. 8.3.2 SPI Mode Operation
        1. 8.3.2.1 Diagnostic Bit Behavior
      3. 8.3.3 Programmable Current Limit
        1. 8.3.3.1 Inrush Current Handling
      4. 8.3.4 DO_EN Feature
      5. 8.3.5 Protection Mechanisms
        1. 8.3.5.1 Overcurrent Protection
        2. 8.3.5.2 Short Circuit Protection
          1. 8.3.5.2.1 VS During Short-to-Ground
        3. 8.3.5.3 Inductive-Load Switching-Off Clamp
        4. 8.3.5.4 Inductive Load Demagnetization
        5. 8.3.5.5 Thermal Shutdown
        6. 8.3.5.6 Undervoltage protection on VS
        7. 8.3.5.7 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
        8. 8.3.5.8 Power-Up and Power-Down Behavior
        9. 8.3.5.9 Reverse Current Blocking
      6. 8.3.6 Diagnostic Mechanisms
        1. 8.3.6.1 Current Sense
          1. 8.3.6.1.1 RSNS Value
            1. 8.3.6.1.1.1 SNS Output Filter
        2. 8.3.6.2 Fault Indication
          1. 8.3.6.2.1 Current Limit Behavior
        3. 8.3.6.3 Short-to-Battery and Open-Load Detection
        4. 8.3.6.4 On-State Wire-Break Detection
        5. 8.3.6.5 Off State Wire-Break Detection
        6. 8.3.6.6 ADC
      7. 8.3.7 LED Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 OFF/POR
      2. 8.4.2 INIT
      3. 8.4.3 Active
    5. 8.5 TPS274C65BS Available Registers List
    6. 8.6 TPS274C65 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IEC 61000-4-5 Surge
        2. 9.2.2.2 Loss of GND
        3. 9.2.2.3 Paralleling Channels
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.6.6 ADC

The device includes an internal ADC that can convert the current sense, temperature sense, input and output voltages. The ADC reference voltage is fixed internally as shown in the electrical characteristics table.

The TPS274C65AS device has a successive approximation 10-bit ADC which can convert multiple channels serially. The ADC can be used to convert the following (but each or all of these can be disabled using SPI register configuration.

  1. Sensed load current. The sense resistor converting the sense current to voltage should be sized such that the max load current (including the 20% over the nominal load value) produces a voltage value at the SNS pin (V_ISNS) that falls roughly at 80% of the ADC range. In this case, if ISNS is at the upper end of the ADC range, the device ADC output indicates that there is an over-load condition, and if ISNS is in the lower end of the ADC range, they know that there is an under-load condition. However, given the very low current values that need to be diagnosed, additional scaling of the V_ISNS voltage or the sensed current may be needed at the very low current limit. Note that the current output occurs only when the switch is enabled ON. The V_ISNS voltage would be sampled by the MUX switch only when the switch is fully ON (switch enable digital signal gated with the ISNS_DELAY signal from) allowing the SNS current to settle. The four-sample average would be done only after the MUX switch is ON. The ADC ISNS reports FF as the output value.

    Equation 8. ADCcurrent in decimal = round[(2number of ADC bits-1)*Iload*RSNS/(KSNS*VADCREF)]

  2. VS/VOUT voltage signals applied to the general purpose ADC pins. Note that the VOUT voltage need only be sensed as a fraction of the VS voltage.

    Equation 9. ADCvoltage in decimal = round[(2number of ADC bits-1)*VS/OUT/30]

    where VS/OUT can be either VS or VOUT

  3. Temperature sensed in each FET.

    Equation 10. ADCtemp in decimal = round[(2number of ADC bits-1)*(0.83-TIC/450)]

    where TIC is in ℃

The ADC’s reference voltage pin is ADREFHI which is generated internally thus making the max voltage convertible to the ADCREFHI. Internally the ADC’s ground reference is connected to the IC GND pin, so externally should be connected to the same pin to minimize the PCB ground shift errors.

The ADC scheduling is round robin with the following order:

  1. ISNS

  2. TSNS

  3. VOUT_SNS

  4. VSNS.

GUID-20231017-SS0I-3LDR-Q6GF-FCMHTMNL7QHQ-low.svg Figure 8-39 ADC Block Diagram