The device senses overcurrent (OC) in both the high-side and low-side power MOSFETs using cycle by cycle detection. OC is detected in the low-side FET by sensing the voltage across the FET while it is on. After the low-side FET turns on, there is a blanking time of approximately 70 ns to allow noise to settle before the OC comparator begins sensing. If the peak current limit is hit, then an OC fault condition is detected which causes the device stops switching and enters hiccup for seven cycles of soft-start CLK frequency. The overcurrent limit is set through a single resistor to ground on the ILIM pin. The ILIM pin can be shorted to ground to reduce BOM component count. When shorted to ground the default current limit is used. Current limits shown in Table 7-7 can be programmed on the ILIM pin.

The device also senses negative overcurrent in the low-side FET by sensing the voltage across the FET while it is on. After the low-side FET turns on, there is a blanking time to allow noise to settle before the OC comparator begins sensing. Once a negative OC fault condition is detected the device stops switching and enters hiccup for seven cycles of soft-start CLK frequency. The negative overcurrent threshold is fixed to a single value.

Overcurrent is detected in the high-side FET by sensing the voltage across the FET while it is on. After the high-side FET turns on, there is a blanking time to allow noise to settle before the OC comparator begins sensing. Once an OC fault condition is detected, the device stops switching and enters hiccup for seven cycles of soft-start CLK frequency. At start-up, the inrush current has the potential of exceeding the peak current limit, thereby causing the device to enter hiccup. To prevent an OC fault trigger at start-up, it is recommended to increase the soft-start time or decrease the load at the output to reduce the inrush current from exceeding the peak current limit. The high-side overcurrent threshold is fixed to a single value. For an application with on-time less than 70 ns, the high-side FET over-current is not guaranteed to enable. In this case, the low-side OC will dominate and protect the load while the output current ramps up gradually. With on-times less than 70 ns and a hard short at the load, the controller loop will extend the on-time to respond to the output voltage drooping, and as a result, both high-side and low-side OC protections will engage to protect the load.