JAJSH47 March 2019 TPS65653-Q1
PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.
The TPS65653-Q1 is capable of providing four levels of protection features:
The TPS65653-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all the pending interrupts are cleared.
When a fault is detected or software requested reset, it is indicated by a RESET_REG_INT interrupt flag in INT_TOP_2 register after next start-up. If the RESET_REG_MASK is set to masked in the OTP, the interrupt is not generated. The mask bit change with I2C does not affect, because the RESET_REG_MASK bit is loaded from OTP during reset sequence.
EVENT | OUTCOME | INTERRUPT BIT | INTERRUPT MASK BIT | STATUS BIT | RECOVERY/INTERRUPT CLEAR |
---|---|---|---|---|---|
Buck current limit triggered | No effect | BUCK_INT
BUCKx_ILIM_INT |
BUCKx_ILIM_MASK | BUCKx_ILIM_STAT | Write 1 to BUCKx_ILIM_INT bit
Interrupt is not cleared if current limit is active |
Buck short circuit (VOUT < 0.35 V at 1 ms after enable) or overload (VOUT decreasing below 0.35 V during operation, 1-ms debounce) | Regulator disable | BUCK_INT
BUCKx_SC_INT |
N/A | N/A | Write 1 to BUCKx_SC_INT bit |
Thermal warning | No effect | TDIE_WARN_INT | TDIE_WARN_MASK | TDIE_WARN_STAT | Write 1 to TDIE_WARN_INT bit
Interrupt is not cleared if temperature is above thermal warning level |
Thermal shutdown | All regulators disabled immediately and GPO and GPO2 are set to low | TDIE_SD_INT | N/A | TDIE_SD_STAT | Write 1 to TDIE_SD_INT bit
Interrupt is not cleared if temperature is above thermal shutdown level |
VANA overvoltage (VANAOVP) | All regulators disabled immediately and GPO and GPO2 are set to low | OVP_INT | N/A | OVP_STAT | Write 1 to OVP_INT bit
Interrupt is not cleared if VANA voltage is above VANAOVP level |
Buck power good, output voltage becomes valid | No effect | BUCK_INT
BUCKx_PG_INT |
BUCKx_PGR_MASK | BUCKx_PG_STAT | Write 1 to BUCKx_PG_INT bit |
Buck power good, output voltage becomes invalid | No effect | BUCK_INT
BUCKx_PG_INT |
BUCKx_PGF_MASK | BUCKx_PG_STAT | Write 1 to BUCKx_PG_INT bit |
PGOOD pin changing from active to inactive state(1) | No effect | PGOOD_INT | PGOOD_MASK | PGOOD_STAT | Write 1 to PGOOD_INT bit |
External clock appears or disappears | No effect to regulators | SYNC_CLK_INT(2) | SYNC_CLK_MASK | SYNC_CLK_STAT | Write 1 to SYNC_CLK_INT bit |
Load current measurement ready | No effect | I_MEAS_INT | I_MEAS_MASK | N/A | Write 1 to I_MEAS_INT bit |
Supply voltage VANAUVLO triggered (VANA falling) | Immediate shutdown, registers reset to default values | N/A | N/A | N/A | N/A |
Supply voltage VANAUVLO triggered (VANA rising) | Startup, registers reset to default values and OTP bits loaded | RESET_REG_INT | RESET_REG_MASK | N/A | Write 1 to RESET_REG_INT bit |
Software requested reset | Immediate shutdown followed by power up, registers reset to default values | RESET_REG_INT | RESET_REG_MASK | N/A | Write 1 to RESET_REG_INT bit |