JAJSH47 March 2019 TPS65653-Q1
PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.
Address: 0x22
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
BUCK1_PGF
_MASK |
BUCK1_PGR
_MASK |
Reserved | BUCK1_ILIM
_MASK |
BUCK0_PGF
_MASK |
BUCK0_PGR
_MASK |
Reserved | BUCK0_ILIM
_MASK |
Bits | Field | Type | Default | Description |
---|---|---|---|---|
7 | BUCK1_PGF_MASK | R/W | X | Masking of Power Good invalid detection for Buck1 power good interrupt (BUCK1_PG_INT in INT_BUCK register):
0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register. |
6 | BUCK1_PGR_MASK | R/W | X | Masking of Power Good valid detection for Buck1 Power Good interrupt (BUCK1_PG_INT in INT_BUCK register):
0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK1_PG_STAT status bit in BUCK_STAT register. |
5 | Reserved | R | 0 | |
4 | BUCK1_ILIM
_MASK |
R/W | X | Masking for Buck1 current limit detection interrupt (BUCK1_ILIM_INT in INT_BUCK register):
0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK1_ILIM_STAT status bit in BUCK_STAT register. |
3 | BUCK0_PGF_MASK | R/W | X | Masking of Power Good invalid detection for Buck0 power good interrupt (BUCK0_PG_INT in INT_BUCK register):
0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register. |
2 | BUCK0_PGR_MASK | R/W | X | Masking of Power Good valid detection for Buck0 power good interrupt (BUCK0_PG_INT in INT_BUCK register):
0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK0_PG_STAT status bit in BUCK_STAT register. |
1 | Reserved | R | 0 | |
0 | BUCK0_ILIM
_MASK |
R/W | X | Masking for Buck0 current limit detection interrupt (BUCK0_ILIM_INT in INT_BUCK register):
0 - Interrupt generated 1 - Interrupt not generated. This bit does not affect BUCK0_ILIM_STAT status bit in BUCK_STAT register. |