JAJSH47 March 2019 TPS65653-Q1
PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.
Address: 0x21
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Reserved | RESET_REG
_MASK |
Bits | Field | Type | Default | Description |
---|---|---|---|---|
7:1 | Reserved | R/W | 000 0000 | |
0 | RESET_REG
_MASK |
R/W | X | Masking for register reset interrupt (RESET_REG_INT in INT_TOP_2 register):
0 - Interrupt generated 1 - Interrupt not generated. This change of this bit by I2C writing has no effect because it will be read from OTP memory during reset. |