JAJSH47 March 2019 TPS65653-Q1
PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.
The TPS65653-Q1 device monitors the input voltage from the VANA pin in standby and active operation modes. If the input voltage rises above VANAOVP voltage level, all the regulators are disabled immediately (without switching ramp, no shutdown delays), pulldown resistors discharge the output voltages if they are enabled (BUCKx_RDIS_EN = 1 in BUCKx_CTRL_1 register), GPOs are set to logic low level, nINT signal is pulled low, OVP_INT bit in INT_TOP_1 register is set to 1, and BUCKx_STAT bit in BUCK_STAT register is set to 0. The host processor clears the interrupt by writing 1 to the OVP_INT bit. If the input voltage is above overvoltage detection level the interrupt is not cleared. The host can read the status of the overvoltage from the OVP_STAT bit in TOP_STAT register. Regulators cannot be enabled as long as the input voltage is above overvoltage detection level or the overvoltage interrupt is pending.