On the DLPLCRC910EVM the trigger input for the
DLPC910 is mediated through the Apps FPGA.
Connecting header J3 APPS_TSTPT7 (Pin 2) to J3 APPS_TSTPT6 (Pin 3) allows the use of SW5 on the AMD Xilinx VC-707
board (lower right corner) to advance patterns when pressed.
Figure 3-6 J3
Apps FPGA Test Point Header Figure 3-7 VC-707 SW5