DLPU124 june 2023
ADDRESS | BITS | DESCRIPTION | TYPE | DEFAULT |
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0x0010 | 0 | pbc_ctlen - enable software control of DMD parameters (PBC) via Apps FPGA. | R/W | 0 |
0 = controlled from SW2 (default) Note: When not enabled software DMD Control
flags are ignored and are controlled by dip switch SW2 |
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1 = controlled from PBC via Apps FPGA PBC registers | ||||
1 | load4 - loads 4 DMD rows for each row input [0 = active; 1 = not active (default)] | R/W | 1 | |
0 = not active | ||||
1 = active | ||||
2 | ns_flip_en - swaps the top of the DMD and the bottom | R/W | 0 | |
0 = not flipped (default) | ||||
1 = flipped Note: This flag changes the following definitions:
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3 | watchdog_en - Enables DMD reset generator timer in the DLPC910 controller | R/W | 1 | |
0 = enabled | ||||
1 = not enabled (default) | ||||
4 | comp_data_en - complements (inverts) the input pixel data (1 → 0 and 0 → 1), sets DMD via SPI | R/W | 0 | |
0 = not inverted (default) | ||||
1 = inverted | ||||
7 | float - sends a specialized reset waveform to the DMD mirrors to release the mirrors and leaves them nominally flat. | R/W | 0 | |
0 = do not float (default) | ||||
1 = float mirrors Note: float is NOT a substitute for a DMD
Park when preparing to shut down the
system. Return to normal operation by setting to 0.
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8 | etrg - enable external trigger for DMD global reset. See Wait for external trigger | R/W | 0 | |
0 = not active (default) | ||||
1 = active |