DLPU124 june 2023
ADDRESS | BITS | DESCRIPTION | TYPE | DEFAULT |
---|---|---|---|---|
0x0000 | 0 | apps_vbus_fsm_timeout_a - swaps the outputs of A with B including serial control output | R/W | 0 |
0 = no timeout occurred | ||||
1 = asserted when a R/W access fails to complete in the allocated timeout duration | ||||
2 | reset_int | R/W | read from firmware | |
0 = no DMD IRQZ event occurred | ||||
1 = DMD IRQZ event occurred Reading provides the current interrupt status: The only existing source for this event is a DMD power fault indicating bias, offset, or reset power supplies have become inactive. The cause of the fault must be determined and resolved prior to a system reset to continue operation. Note: The bit must be
cleared after a power cycle or a reset to the DLPC910. Writing a
1 clears the interrupt bit via software. |