5.3.4 Thermal Information
THERMAL METRIC(1) |
LMK04616 |
UNIT |
ZCR (NFBGA) |
176 PINS |
RθJA |
Junction-to-ambient thermal resistance(2) |
|
45.0 |
°C/W |
14-layer, 200-mm × 150-mm board, 144 thermal vias, airflow = 0 LFM |
23.3 |
RθJC(top) |
Junction-to-case (top) thermal resistance(3) |
|
12.5 |
°C/W |
14-layer, 200-mm × 150-mm board, 144 thermal vias, airflow = 0 LFM |
0.1 |
RθJB |
Junction-to-board thermal resistance(4) |
|
25.2 |
°C/W |
14-layer, 200-mm × 150-mm board, 144 thermal vias, airflow = 0 LFM |
18.3 |
ψJT |
Junction-to-top characterization parameter(5) |
|
0.2 |
°C/W |
8-layer, 200-mm × 150-mm board, 21 thermal vias, airflow = 0 LFM |
27.7 |
ψJB |
Junction-to-board characterization parameter(6) |
|
24.9 |
°C/W |
8-layer, 200-mm × 150-mm board, 21 thermal vias, airflow = 0 LFM |
0.1 |
RθJC(bot) |
Junction-to-case (bottom) thermal resistance(7) |
|
n/a |
°C/W |
8-layer, 200-mm × 150-mm board, 21 thermal vias, airflow = 0 LFM |
21.5 |
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.