SBOU024C august 2004 – july 2023 PGA309
In Stand-Alone Mode (see Chapter 3, Operating Modes), the PGA309 accesses the external EEPROM in a different fashion than that presented for the One-Wire Interface Initiated Two-Wire Transactions. If all other POR conditions have been met to allow a PGA309 to allow access to a properly programmed external EEPROM, the PGA309 will first access the first part of the external EEPROM (configuration register data) as shown in Figure 4-11.
If the Checksum1 is correct and the PGA309 is triggered by the Temp ADC to read the second part of the EEPROM, it will proceed as shown in Figure 4-12. If the One-Wire disable bit, OWD, bit 15, in Register 4 is set to ‘1’, initial POR is completed, and a valid Checksum2 is received, the One-Wire interface will be disabled, the PRG pin becomes high impedance, and One-Wire communication cannot take place unless power is cycled. This is necessary to allow for direct connection of the PRG pin to VOUT.