SBOU024C august 2004 – july 2023 PGA309
There are two digital interfaces on the PGA309. The PRG pin uses a One-Wire, UART-compatible interface with bit rates from 4.8Kbits/s to 38.4Kbits/s. The SDA and SCL pins together form an industry standard Two-Wire interface at clock rates from 1kHz to 400kHz. The external EEPROM uses the Two-Wire interface. Communication to the PGA309 internal registers, as well as to the external EEPROM, for programming and readback can be conducted through either digital interface.
It is also possible to connect the One-Wire communication pin, PRG, to the VOUT pin in true three-wire sensor modules and still allow for programming. In this mode, the PGA309 Output Amplifier may be enabled for a set time period and then disabled again to allow sharing of the PRG pin with the VOUT connection. This allows for both digital calibration and analog readback during sensor calibration in a three-wire sensor module.
The Two-Wire interface has timeout mechanisms to prevent bus lockup from occurring. The Two-Wire master controller in the PGA309 has a mode that attempts to free up a stuck-at-zero SDA line by issuing SCL pulses, even when the bus is not indicated as idle after the timeout period has expired. The timeout will only apply when the master portion of the PGA309 is attempting to initiate a Two-Wire communication.