SLAAET8A April   2025  – December 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0G3529-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EMC and EMC Standards
    1. 2.1 EMC
      1. 2.1.1 EMS
      2. 2.1.2 EMI
    2. 2.2 EMC Standards
      1. 2.2.1 EMC Standards Category
    3. 2.3 EMC and IC Electrical Reliability in TI
  6. 3EMC Improvement Guidelines Summary
    1. 3.1 PCB Design Guidelines
    2. 3.2 Firmware Guidelines
  7. 4EMC Improvement Features on MSPM0
    1. 4.1 Susceptibility Protection Features
      1. 4.1.1 POR and BOR
      2. 4.1.2 NMI and Hard Fault
      3. 4.1.3 I/O ESD and Settings
    2. 4.2 Emission Reduction Features
      1. 4.2.1 Clock Source
      2. 4.2.2 Power Modes
      3. 4.2.3 Package
  8. 5Analysis for EMS Test
    1. 5.1 Root Cause Analysis
      1. 5.1.1 Permanent Damage
      2. 5.1.2 Recoverable Malfunction
    2. 5.2 Debug Flow
  9. 6Analysis for EMI Test
    1. 6.1 Root Cause Analysis
      1. 6.1.1 Power Line
      2. 6.1.2 External Vcore
    2. 6.2 Debug Flow
  10. 7Summary
  11. 8References
  12. 9Revision History

6.1.2 External Vcore

The power management unit (PMU) of MSPM0 uses an on-chip, configurable, low-dropout LDO to generate a 1.35V supply rail to power the device core. In general, the core regulator output (VCORE) supplies power to the core logic, which includes the CPU, digital peripherals and the device memory. For some MSPM0 devices, the internal LDO requires an external capacitor (CVCORE) which is connected between the device VCORE pin and VSS (ground). For some MSPM0 devices, the coupling capacitor is integrated into the IC.

Power Module of MSPM0GFigure 6-4 Power Module of MSPM0G

The LDO cannot respond instantaneously to transient conditions. A delay occurs before the current through the pass element adjusts to the increased load. During this delay time, the output capacitor is left to supply the entire transient current. Because of this, the amount of output capacitance and the associated parasitic elements greatly impact the transient response of the LDO circuit. Compared with the internal capacitor usage, the external capacitor usage is more sensitive to the parasitic inductance and causes bad performance on the load-transient response for the power noise generated by the high speed digital circuits. A conducted noise example on Vcore is shown in Figure 6-5. In this example, CVCORE is 0.47uF and MSPM0 runs with one NOP.

Conducted Noise at Vcore on MSPM0LFigure 6-5 Conducted Noise at Vcore on MSPM0L

To improve the EMI performance of the MCU, a low-ESR capacitor is suggested to reduce the parasitic inductance influence. Besides the suggested 0.47uF capacitors, users can add more capacitors with different capacitance to cover the target frequency range. For more information about output capacitor influence on LDO EMI performance, refer to the EMC Measures for LDOs and Understanding the load-transient response of LDOs analog design journal.