SLAAET8A April   2025  – December 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0G3529-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EMC and EMC Standards
    1. 2.1 EMC
      1. 2.1.1 EMS
      2. 2.1.2 EMI
    2. 2.2 EMC Standards
      1. 2.2.1 EMC Standards Category
    3. 2.3 EMC and IC Electrical Reliability in TI
  6. 3EMC Improvement Guidelines Summary
    1. 3.1 PCB Design Guidelines
    2. 3.2 Firmware Guidelines
  7. 4EMC Improvement Features on MSPM0
    1. 4.1 Susceptibility Protection Features
      1. 4.1.1 POR and BOR
      2. 4.1.2 NMI and Hard Fault
      3. 4.1.3 I/O ESD and Settings
    2. 4.2 Emission Reduction Features
      1. 4.2.1 Clock Source
      2. 4.2.2 Power Modes
      3. 4.2.3 Package
  8. 5Analysis for EMS Test
    1. 5.1 Root Cause Analysis
      1. 5.1.1 Permanent Damage
      2. 5.1.2 Recoverable Malfunction
    2. 5.2 Debug Flow
  9. 6Analysis for EMI Test
    1. 6.1 Root Cause Analysis
      1. 6.1.1 Power Line
      2. 6.1.2 External Vcore
    2. 6.2 Debug Flow
  10. 7Summary
  11. 8References
  12. 9Revision History

3.1 PCB Design Guidelines

PCB optimization is a key part for EMC improvement. The suggestions for optimization are presented as a check list format. All these suggestions are valid for both EMI and EMS.

Table 3-1 PCB Design Guidelines
ItemSuggestions CategorySuggestions
Schematic DesignMSPM0 minimum system
  • Follow the guidance in the Schematic section of the data sheet to add resistors and capacitors on power supply, Vcore and Reset. An example is shown in Figure 3-1.
EMC protection components
  • Add EMC protection components shown in Table 3-2 at I/O ports and power inputs for more robust protection
PCB LayoutPower
  • Place decoupling capacitors to be closed to the MCU and the 100pF capacitor is closest.
  • VDD line goes into the MCU by following this sequence: branch point->bypass capacitors-> MCU
Ground
  • Implement star grounding for mixed-signal systems
  • Use continuous ground planes (avoid splits under high-speed traces)
  • Add ground-filled zones in unused board areas
  • Add a solid GND under the MCU to reduce radiative noise
  • Place the GND pattern around the PCB perimeter and do not run the power supply (VDD) or signal lines
  • The power supply and GND pattern corners need to be 45 degrees or curved
  • Ground pins must be evenly distributed across all connectors
Oscillator
  • Reduce external oscillator loop to MCU GND pin
  • Surrounding oscillator wiring with a GND pattern
  • Separate the Oscillator GND and PCB GND to reduce radiative noise
General signals
  • Reduce trace lengths/loop areas (critical for clock and high-speed signals)
  • Signals must be curved at 45 degrees

Table 3-2 are the common used passive protection components to improve the EMC. If users want to have a deep understanding for the influence of passive protection components and PCB design on EMC improvement, then the Noise Suppression Basic Course provided by Murata is a good learning resource.

Table 3-2 Passive Protection Components
CategoryMC CategoryWhen to UseKey AdvantagesCritical ParametersDesign Tips
Resistor (Series)EMS, EMIHigh-frequency circuits requiring current controlLimits spikes, absorbs EMI, low inductanceResistance value, parasitic inductance (<1 nH)Use metal film; avoid carbon composition
Clamping DiodesEMSESD-sensitive high-speed interfaces (USB, HDMI)Ultra-fast response (< 1ns), low clamping voltageClamping voltage, peak pulse current, capacitancePlace near protected IC; pair with series resistors
CapacitorEMS, EMINoise filtering or energy bufferingCeramic (high-frequency), electrolytic (bulk)SRF, voltage rating, capacitanceMatch SRF to noise; avoid overlapping SRFs
TVS DiodeEMSHigh-energy surges (lightning, inductive loads)Ultra-fast clamping (< 1ps), handles 10kA surgesReverse standoff voltage, clamping voltageStandoff voltage > operating voltage by 20%
Ferrite BeadEMIGHz-range noise on power or data linesFrequency-specific attenuation, no DC lossImpedance at target frequency, DCRCheck impedance under DC bias
Common-Mode ChokeEMS/EMICommon-mode noise in differential lines (CAN, USB)Blocks noise without signal distortionImpedance (for example, 600Ω at 100MHz), current ratingBalance winding inductance; minimize parasitics
EMI Filter (LC/Pi/T)EMS/EMIBroadband noise in power/signal linesMultistage topology (Pi/T for high/low impedance)Cutoff frequency, insertion lossPi-filter for power lines; T-filter for signals
Gas Discharge TubeEMSExtreme surges (telecom, lightning)Handles 20kA surges, low capacitance, durableBreakdown voltage, response timePair with TVS diodes for multi-stage protection

Here is an example of MSPM0 schematic design. For more description, refer to the data sheet of the specific MSPM0.


Basic Application Schematic of MSPM0G

Figure 3-1 Basic Application Schematic of MSPM0G