SLAAET8A April   2025  – December 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0G3529-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EMC and EMC Standards
    1. 2.1 EMC
      1. 2.1.1 EMS
      2. 2.1.2 EMI
    2. 2.2 EMC Standards
      1. 2.2.1 EMC Standards Category
    3. 2.3 EMC and IC Electrical Reliability in TI
  6. 3EMC Improvement Guidelines Summary
    1. 3.1 PCB Design Guidelines
    2. 3.2 Firmware Guidelines
  7. 4EMC Improvement Features on MSPM0
    1. 4.1 Susceptibility Protection Features
      1. 4.1.1 POR and BOR
      2. 4.1.2 NMI and Hard Fault
      3. 4.1.3 I/O ESD and Settings
    2. 4.2 Emission Reduction Features
      1. 4.2.1 Clock Source
      2. 4.2.2 Power Modes
      3. 4.2.3 Package
  8. 5Analysis for EMS Test
    1. 5.1 Root Cause Analysis
      1. 5.1.1 Permanent Damage
      2. 5.1.2 Recoverable Malfunction
    2. 5.2 Debug Flow
  9. 6Analysis for EMI Test
    1. 6.1 Root Cause Analysis
      1. 6.1.1 Power Line
      2. 6.1.2 External Vcore
    2. 6.2 Debug Flow
  10. 7Summary
  11. 8References
  12. 9Revision History

4.1.3 I/O ESD and Settings

Microcontroller input and output circuitry has been designed to take ESD and latch-up problems into account. However, self-protection is limited, especially when exposed to illegal voltages and high-current injections in EMS tests. TI strongly recommends to implement additional hardware protection if the features below do not work or the IO configuration cannot be satisfied.

Figure 4-3 shows the I/O structure in MSPM0. There are two possible routes to dissipate the energy from illegal voltages and high-current injections. The first and the default route is the two ESD diodes. The second is the P-channel Metal-Oxide-Semiconductor (PMOS) and N-channel Metal-Oxide-Semiconductor (NMOS) near the ESD diodes.

IO Structure of MSPM0GFigure 4-3 IO Structure of MSPM0G

The ESD diodes are triggered if a signal is applied that exceeds maximum input voltage range (-0.3V ≃ VCC+0.3V). The ESD diodes can withstand instantaneous ampere-level currents generated during typical electrostatic discharge events (per HBM or CDM standards). This ESD structure is also helpful to defend the illegal voltages and high-current injections in EMS tests.

For full featured IOs, with the output driver logic control, the PMOS and NMOS can also be a path to release the electrical stress. However, for open-drain IOs, the pull-up clamping diode and the PMOS do not exist yet. When the positive electrical stress happens, there is no route to release. The suggestions with different I/O settings are shown in Table 4-3.

Table 4-3 EMS Influence with IO Setting
IO TypeIO SettingIO StatusInfluenceEMS Protection
General IO

GPIO output and peripheral output (for example, UART)

Output mode

MOS and ESD structure release EMC noise

Best protection

Default setting and analog functions

Hiz mode

ESD structure release EMC noise

Good protection

GPIO Input And Peripheral Input (for example, UART)

Input mode

ESD structure release EMC noise

Can introduce noise into MCU internal circuit

Good Protection

Open-drain IO

GPIO and peripheral output

Output mode

No route to dissipate the positive energy

Risk for positive noise and can need external protection

Default setting and analog functions

Hiz mode

No route to dissipate the positive energy

Risk for positive noise and can need external protection

GPIO input/ peripheral input (for example, UART)

Input mode

No route to dissipate the positive energy

Risk for positive noise and can need external protection