SLAAET8A April   2025  – December 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0G3529-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EMC and EMC Standards
    1. 2.1 EMC
      1. 2.1.1 EMS
      2. 2.1.2 EMI
    2. 2.2 EMC Standards
      1. 2.2.1 EMC Standards Category
    3. 2.3 EMC and IC Electrical Reliability in TI
  6. 3EMC Improvement Guidelines Summary
    1. 3.1 PCB Design Guidelines
    2. 3.2 Firmware Guidelines
  7. 4EMC Improvement Features on MSPM0
    1. 4.1 Susceptibility Protection Features
      1. 4.1.1 POR and BOR
      2. 4.1.2 NMI and Hard Fault
      3. 4.1.3 I/O ESD and Settings
    2. 4.2 Emission Reduction Features
      1. 4.2.1 Clock Source
      2. 4.2.2 Power Modes
      3. 4.2.3 Package
  8. 5Analysis for EMS Test
    1. 5.1 Root Cause Analysis
      1. 5.1.1 Permanent Damage
      2. 5.1.2 Recoverable Malfunction
    2. 5.2 Debug Flow
  9. 6Analysis for EMI Test
    1. 6.1 Root Cause Analysis
      1. 6.1.1 Power Line
      2. 6.1.2 External Vcore
    2. 6.2 Debug Flow
  10. 7Summary
  11. 8References
  12. 9Revision History

5.1.2 Recoverable Malfunction

For the recoverable malfunction, MSPM0 devices include several diagnostic mechanisms to detect errors at runtime. Table 5-4 lists error sources and the corresponding handling mechanism. This can be used to give additional analysis information in EMS failure analysis.

Table 5-4 Error Sources and Handling Mechanisms
Error SourceErrorHandling Mechanism
Flash (if device has ECC)Non-correctable ECC error (if device has ECC)
  • For a CPU or DMA request, a FLASHDED nonmaskable interrupt is generated to the processor or a SYSRST is generated depending on configuration of the FLASHECCRSTDIS bit
  • The FLASHDED sticky bit is set in the SYSSTATUS register in SYSCTL
Correctable ECC error (if device has ECC)
  • A FLASHSEC interrupt is also generated in SYSCTL
  • The FLASHSEC sticky bit is set in the SYSSTATUS register in SYSCTL
SRAMNon-correctable ECC error (if device has ECC)
  • An SRAMDED nonmaskable interrupt is generated to the processor
Correctable ECC error (if device has ECC)
  • A SYSCTL SRAMSED interrupt is generated to the processor
Parity error (if device has parity)
  • Nonmaskable interrupt is generated to the processor if the request was from the CPU
  • DMA data error interrupt is generated if the request was from the DMA
Address error on CPU access
  • A hard fault is generated in the CPU
Address error on DMA access
  • A DMA address error interrupt is generated in the DMA controller
ECC error on CAN SRAM (if device has CAN-FD)
  • An interrupt is generated in the CAN-FD peripheral
SHUTDNSTOREx Memory (if present)Parity error
  • A POR is generated
CKMMCLK failure
  • A BOOTRST is generated
LFCLK failure (if present)
  • A BOOTRST is generated if LFCLK is sourcing MCLK
  • An LFCLKFAIL nonmaskable interrupt is generated in the SYSCTL NMI registers.
CPUSS (if device has MPU)Memory protection unit violation
  • A hard fault is generated in the CPU
WWDTWWDT0 violation
  • A BOOTRST is generated or a nonmaskable interrupt is generated in the SYSCTL NMI registers depending on configuration of the WWDTLP0RSTDIS bit
WWDT1 violation (if present)
  • A BOOTRST is generated or a nonmaskable interrupt is generated in the SYSCTL NMI registers depending on configuration of the WWDTLP1RSTDIS bit
PMUTrim parity error
  • A POR is generated
POR0- supply error
  • A POR is generated
BOR0- supply error
  • A BOR is generated
BOR1/2/3- supply error
  • A BORLVL nonmaskable interrupt is generated in the SYSCTL NMI registers
CPUSSMemory protection unit violation (if present)
  • A hard fault is generated in the CPU

If MCU resets abnormally, then users can get the reset source information from RSTCAUSE register using DL_SYSCTL_getResetCause() software function. Then search the RSTCAUSE table to know the reset source, as shown in Table 5-5.

Table 5-5 RSTCAUSE Field Descriptions of MSPM0G
BitFieldTypeResetDescription
31-5RESERVEDR0h
4-0IDRC0hID is a read-to-clear field which indicates the lowest level reset cause since the last read.
  • 0h = No reset since last read
  • 1h = POR- violation, SHUTDNSTOREx or PMU trim parity fault
  • 2h = NRST triggered POR (>1s hold)
  • 3h = Software triggered POR
  • 4h = BOR0- violation
  • 5h = SHUTDOWN mode exit
  • 8h = Non-PMU trim parity fault
  • 9h = Fatal clock failure
  • Ah = Software triggered BOOTRST
  • Ch = NRST triggered BOOTRST (<1s hold)
  • 10h = BSL exit
  • 11h = BSL entry
  • 12h = WWDT0 violation
  • 13h = WWDT1 violation
  • 14h = Flash uncorrectable ECC error
  • 15h = CPULOCK violation
  • 1Ah = Debug triggered SYSRST
  • 1Bh = Software triggered SYSRST
  • 1Ch = Debug triggered CPURST
  • 1Dh = Software triggered CPURST

If reset does not happen and MCU only functions abnormally, then the MCU is trapped in default handler. To know the exact interrupt source, users can read IPSR register, using __get_IPSR() software function. An example is shown in Table 5-6. For the detailed interrupt source, refer to the MSPM0 Platform Processor Interrupt and Exception Table section in the device-specific TRM. Before CPU jumps to default handler, it will store current Core Register status, and push these registers value into Stack. Check the stack content to get the PC value when the interrupt occurs. Please check Cortex-M0+ DevicesGeneric User Guide for the exception entry and return flow.

Table 5-6 MSPM0 Platform Processor Interrupt and Exception
Exception NumberNVIC NumberPriority GroupException or InterruptVector Table AddressVector Description
----0x0000.0000Stack pointer
1--3Reset0x0000.0004Reset vector
2--2NMI0x0000.0008NMI handler
3--1Hard fault0x0000.000CHard fault handler