SLLA305A May   2010  – September 2023 ESD441 , TPD12S015 , TPD12S015A , TPD12S016 , TPD12S520 , TPD12S521 , TPD13S523 , TPD1E05U06 , TPD1E10B06 , TPD1E10B09 , TPD1E6B06 , TPD1S414 , TPD1S514 , TPD2E001 , TPD2E001-Q1 , TPD2E009 , TPD2E1B06 , TPD2E2U06 , TPD2E2U06-Q1 , TPD2EUSB30 , TPD2EUSB30A , TPD2S017 , TPD3F303 , TPD3S014 , TPD3S044 , TPD4E001 , TPD4E001-Q1 , TPD4E004 , TPD4E02B04 , TPD4E05U06 , TPD4E05U06-Q1 , TPD4E101 , TPD4E1B06 , TPD4E1U06 , TPD4E6B06 , TPD4EUSB30 , TPD4S010 , TPD4S012 , TPD4S014 , TPD4S1394 , TPD4S214 , TPD5E003 , TPD5S115 , TPD5S116 , TPD6E001 , TPD6E004 , TPD6E05U06 , TPD6F002 , TPD6F002-Q1 , TPD6F003 , TPD7S019 , TPD8E003 , TPD8F003 , TPD8S009

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Device Summary
  6. 3Pin Configuration and Functions
  7. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings - JEDEC
    3. 4.3 ESD Ratings - AEC
    4. 4.4 ESD Ratings - IEC
    5. 4.5 ESD Ratings - ISO
    6. 4.6 Recommended Operating Conditions
    7. 4.7 Thermal Information
    8. 4.8 Electrical Characteristics
      1. 4.8.1 Reverse Standoff Voltage (VRWM)
      2. 4.8.2 Breakdown Voltage (VBR)
      3. 4.8.3 Leakage Current (ILEAK)
      4. 4.8.4 Dynamic Resistance (RDYN)
      5. 4.8.5 Line Capacitance (CL)
      6. 4.8.6 Clamping Voltage (VCLAMP)
    9. 4.9 Typical Characteristics
      1. 4.9.1 TLP Plot
      2. 4.9.2 ± 8kV Clamped IEC Waveform
      3. 4.9.3 Capacitance vs. Bias Voltage
      4. 4.9.4 Leakage Current vs. Temperature
      5. 4.9.5 Capacitance vs. Temperature
      6. 4.9.6 Insertion Loss
  8. 5Summary
  9. 6References
  10. 7Revision History

TLP Plot

Transmission line pulse (TLP) plots test the behavior of a device in the current and time domain during an ESD event. The pulse width and rise time can easily be changed, but typically, the testing involves a rectangular current pulse of 1 to 5-ns rise time and 100-ns pulse width. The TLP plot provides important parameters, the breakdown voltage and the dynamic resistance of the clamp. As mentioned in Section 4.8.6, the clamping voltage can be derived from the TLP plot if the clamping voltage is not explicitly provided in the data sheet. An example is shown from the ESD2CANFD24 data sheet. For this device, looking at 16-A, the clamping voltage is estimated to be 36-V. The device does experience snap-back which is a technique used to reduce the overall voltage drop during an ESD event. Since ESD2CANFD24 is a bi-directional diode, the positive and negative TLP plots are almost identical, this is not the case for uni-directional diodes.

GUID-508A5AE9-DEA4-4FAE-A792-17518CD14D60-low.svgFigure 4-2 Positive TLP Curve
GUID-8728CB62-C7FA-400E-899B-7F0C885492A6-low.svgFigure 4-3 Negative TLP Curve